Simulation Results: edn/edn0

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.70 %
  • code
  • 95.55 %
  • assert
  • 98.70 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.79 %
  • toggle
  • 97.12 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
96.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.470s 17.864us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.310s 35.563us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.280s 26.297us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.390s 165.939us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.320s 18.141us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.480s 87.881us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.280s 26.297us 5 5 100.00
edn_csr_aliasing 1.320s 18.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 7.370s 600.447us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 7.370s 600.447us 100 100 100.00
genbits 100 100 100.00
edn_genbits 7.370s 600.447us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.590s 27.577us 20 20 100.00
alerts 200 200 100.00
edn_alert 2.130s 400.493us 200 200 100.00
errs 100 100 100.00
edn_err 1.870s 31.033us 100 100 100.00
disable 100 100 100.00
edn_disable 1.380s 13.349us 50 50 100.00
edn_disable_auto_req_mode 1.920s 52.711us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 8.230s 460.553us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.350s 17.684us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.380s 67.466us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.090s 147.167us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.090s 147.167us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.310s 35.563us 1 1 100.00
edn_csr_rw 1.280s 26.297us 5 5 100.00
edn_csr_aliasing 1.320s 18.141us 1 1 100.00
edn_same_csr_outstanding 1.670s 115.007us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.310s 35.563us 1 1 100.00
edn_csr_rw 1.280s 26.297us 5 5 100.00
edn_csr_aliasing 1.320s 18.141us 1 1 100.00
edn_same_csr_outstanding 1.670s 115.007us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 13.910s 761.328us 5 5 100.00
edn_tl_intg_err 3.990s 289.347us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.410s 55.066us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 2.130s 400.493us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 13.910s 761.328us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 13.910s 761.328us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 13.910s 761.328us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 13.910s 761.328us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 2.130s 400.493us 200 200 100.00
edn_sec_cm 13.910s 761.328us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 2.130s 400.493us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.990s 289.347us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 30 96.67
edn_stress_all_with_rand_reset 112.460s 3954.214us 29 30 96.67

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 25090688590485968147508607032804333548355786504156606009569051798566513195628 157
UVM_INFO @ 11135072612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---