Simulation Results: edn/edn1

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.24 %
  • code
  • 96.15 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.92 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
99.84%
V2S
100.00%
V3
96.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.280s 18.768us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.250s 61.384us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.160s 25.038us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 7.940s 2791.914us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.220s 50.975us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.970s 31.864us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.160s 25.038us 5 5 100.00
edn_csr_aliasing 1.220s 50.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 10.040s 965.750us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 10.040s 965.750us 100 100 100.00
genbits 100 100 100.00
edn_genbits 10.040s 965.750us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.500s 23.110us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.790s 278.727us 200 200 100.00
errs 99 100 99.00
edn_err 105.540s 10000.985us 99 100 99.00
disable 100 100 100.00
edn_disable 1.260s 13.357us 50 50 100.00
edn_disable_auto_req_mode 1.790s 51.872us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 8.290s 386.722us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.190s 14.643us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.270s 168.166us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.990s 150.715us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.990s 150.715us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.250s 61.384us 1 1 100.00
edn_csr_rw 1.160s 25.038us 5 5 100.00
edn_csr_aliasing 1.220s 50.975us 1 1 100.00
edn_same_csr_outstanding 1.910s 44.430us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.250s 61.384us 1 1 100.00
edn_csr_rw 1.160s 25.038us 5 5 100.00
edn_csr_aliasing 1.220s 50.975us 1 1 100.00
edn_same_csr_outstanding 1.910s 44.430us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.470s 1024.147us 5 5 100.00
edn_tl_intg_err 3.510s 161.760us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.290s 30.465us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.790s 278.727us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.470s 1024.147us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.470s 1024.147us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.470s 1024.147us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.470s 1024.147us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.790s 278.727us 200 200 100.00
edn_sec_cm 7.470s 1024.147us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.790s 278.727us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.510s 161.760us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 30 96.67
edn_stress_all_with_rand_reset 135.830s 11803.967us 29 30 96.67

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1209) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
edn_stress_all_with_rand_reset 115048392781134036812174141923412405384702016385948917275753575251576873029135 275
UVM_INFO @ 2653174223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_err_vseq] wait timeout occurred! 1 test run
edn_err 108485614340587375218652304406417392614622964359920260293947199142731300573763 127
UVM_INFO @ 10000985472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---