Simulation Results: hmac

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.19 %
  • code
  • 88.29 %
  • assert
  • 97.60 %
  • func
  • 99.68 %
  • line
  • 99.64 %
  • branch
  • 99.35 %
  • cond
  • 96.30 %
  • toggle
  • 46.17 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 15.750s 492.867us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 23.021us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.130s 28.717us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.230s 621.755us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.420s 75.231us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 1.680s 119.743us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.130s 28.717us 5 5 100.00
hmac_csr_aliasing 1.420s 75.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 96.240s 9537.826us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 116.670s 3267.796us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 271.150s 20273.548us 30 30 100.00
hmac_test_sha384_vectors 626.410s 21161.253us 75 75 100.00
hmac_test_sha512_vectors 608.520s 29763.583us 75 75 100.00
hmac_test_hmac256_vectors 15.690s 1047.790us 50 50 100.00
hmac_test_hmac384_vectors 17.490s 2057.768us 60 60 100.00
hmac_test_hmac512_vectors 19.200s 1001.120us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 39.460s 3865.832us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 2798.770s 17675.799us 10 10 100.00
error 10 10 100.00
hmac_error 88.600s 5378.936us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 168.360s 39187.031us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 15.750s 492.867us 10 10 100.00
hmac_long_msg 96.240s 9537.826us 10 10 100.00
hmac_back_pressure 116.670s 3267.796us 25 25 100.00
hmac_datapath_stress 2798.770s 17675.799us 10 10 100.00
hmac_burst_wr 39.460s 3865.832us 50 50 100.00
hmac_stress_all 4259.310s 61461.798us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 15.750s 492.867us 10 10 100.00
hmac_long_msg 96.240s 9537.826us 10 10 100.00
hmac_back_pressure 116.670s 3267.796us 25 25 100.00
hmac_datapath_stress 2798.770s 17675.799us 10 10 100.00
hmac_wipe_secret 168.360s 39187.031us 10 10 100.00
hmac_test_sha256_vectors 271.150s 20273.548us 30 30 100.00
hmac_test_sha384_vectors 626.410s 21161.253us 75 75 100.00
hmac_test_sha512_vectors 608.520s 29763.583us 75 75 100.00
hmac_test_hmac256_vectors 15.690s 1047.790us 50 50 100.00
hmac_test_hmac384_vectors 17.490s 2057.768us 60 60 100.00
hmac_test_hmac512_vectors 19.200s 1001.120us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 15.750s 492.867us 10 10 100.00
hmac_long_msg 96.240s 9537.826us 10 10 100.00
hmac_back_pressure 116.670s 3267.796us 25 25 100.00
hmac_datapath_stress 2798.770s 17675.799us 10 10 100.00
hmac_burst_wr 39.460s 3865.832us 50 50 100.00
hmac_error 88.600s 5378.936us 10 10 100.00
hmac_wipe_secret 168.360s 39187.031us 10 10 100.00
hmac_test_sha256_vectors 271.150s 20273.548us 30 30 100.00
hmac_test_sha384_vectors 626.410s 21161.253us 75 75 100.00
hmac_test_sha512_vectors 608.520s 29763.583us 75 75 100.00
hmac_test_hmac256_vectors 15.690s 1047.790us 50 50 100.00
hmac_test_hmac384_vectors 17.490s 2057.768us 60 60 100.00
hmac_test_hmac512_vectors 19.200s 1001.120us 75 75 100.00
hmac_stress_all 4259.310s 61461.798us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 4259.310s 61461.798us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.900s 26.115us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.940s 92.338us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 5.520s 255.578us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 5.520s 255.578us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.000s 23.021us 1 1 100.00
hmac_csr_rw 1.130s 28.717us 5 5 100.00
hmac_csr_aliasing 1.420s 75.231us 1 1 100.00
hmac_same_csr_outstanding 2.500s 45.990us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.000s 23.021us 1 1 100.00
hmac_csr_rw 1.130s 28.717us 5 5 100.00
hmac_csr_aliasing 1.420s 75.231us 1 1 100.00
hmac_same_csr_outstanding 2.500s 45.990us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.330s 62.318us 5 5 100.00
hmac_tl_intg_err 4.820s 247.288us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 4.820s 247.288us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 15.750s 492.867us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.990s 929.051us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 402.500s 6144.563us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.790s 124.578us 1 1 100.00