Simulation Results: lc_ctrl/volatile_unlock_disabled

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.21 %
  • code
  • 85.73 %
  • assert
  • 94.83 %
  • func
  • 96.06 %
  • line
  • 97.28 %
  • branch
  • 94.05 %
  • cond
  • 81.70 %
  • toggle
  • 88.33 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.530s 198.626us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.120s 103.409us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.260s 58.522us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.010s 37.630us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.250s 20.962us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.820s 145.640us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.260s 58.522us 5 5 100.00
lc_ctrl_csr_aliasing 1.250s 20.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 10.290s 2196.220us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.050s 1150.202us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.200s 14.409us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 2.650s 276.507us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 13.550s 4948.985us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 12.850s 2294.443us 20 20 100.00
security_escalation 140 140 100.00
lc_ctrl_state_failure 13.550s 4948.985us 20 20 100.00
lc_ctrl_prog_failure 2.650s 276.507us 20 20 100.00
lc_ctrl_errors 12.850s 2294.443us 20 20 100.00
lc_ctrl_security_escalation 10.440s 525.718us 20 20 100.00
lc_ctrl_jtag_state_failure 41.780s 2432.553us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.490s 4900.949us 20 20 100.00
lc_ctrl_jtag_errors 58.630s 29074.177us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 7.660s 636.263us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.520s 3292.284us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.490s 4900.949us 20 20 100.00
lc_ctrl_jtag_errors 58.630s 29074.177us 20 20 100.00
lc_ctrl_jtag_access 14.180s 1233.405us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 21.970s 1082.322us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.080s 359.029us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.050s 186.273us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 19.920s 2257.978us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 4.070s 250.262us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.820s 194.612us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.300s 258.396us 10 10 100.00
lc_ctrl_jtag_alert_test 2.300s 95.194us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 16.730s 1202.135us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.400s 18.086us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 179.730s 10043.493us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.440s 29.041us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 3.790s 541.059us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 3.790s 541.059us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.120s 103.409us 1 1 100.00
lc_ctrl_csr_rw 1.260s 58.522us 5 5 100.00
lc_ctrl_csr_aliasing 1.250s 20.962us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.470s 24.499us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.120s 103.409us 1 1 100.00
lc_ctrl_csr_rw 1.260s 58.522us 5 5 100.00
lc_ctrl_csr_aliasing 1.250s 20.962us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.470s 24.499us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.720s 349.816us 5 5 100.00
lc_ctrl_tl_intg_err 3.920s 384.185us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.920s 384.185us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.050s 1150.202us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 13.550s 4948.985us 20 20 100.00
lc_ctrl_sec_cm 10.720s 349.816us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 13.550s 4948.985us 20 20 100.00
lc_ctrl_sec_cm 10.720s 349.816us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.550s 4948.985us 20 20 100.00
lc_ctrl_sec_cm 10.720s 349.816us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.550s 4948.985us 20 20 100.00
lc_ctrl_sec_cm 10.720s 349.816us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 13.550s 4948.985us 20 20 100.00
lc_ctrl_sec_cm 10.720s 349.816us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.550s 4948.985us 20 20 100.00
lc_ctrl_sec_cm 10.720s 349.816us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.550s 4948.985us 20 20 100.00
lc_ctrl_sec_cm 10.720s 349.816us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 13.550s 4948.985us 20 20 100.00
lc_ctrl_sec_cm 10.720s 349.816us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 10.440s 525.718us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 10.290s 2196.220us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.520s 3292.284us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.370s 929.122us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.370s 929.122us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 7.940s 827.544us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 6.630s 4138.767us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 6.630s 4138.767us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
lc_ctrl_stress_all_with_rand_reset 85.620s 4862.685us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
lc_ctrl_stress_all_with_rand_reset 6183131578710118821683376394300853845513513795658123999455514798487181184561 1972
UVM_INFO @ 7612014696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51066272262398383340108163411044504139303322403534928259246653382803415482511 10979
UVM_INFO @ 3201457493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65367131578317996448406846188734963830994275738654346850231780392530694467683 7654
UVM_INFO @ 48232508239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 55543684673697825512507425533614483234223916391252415395566827437401543230712 1258
UVM_INFO @ 1383390597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93184144523768100332978247448612653336437020555008397941191879106560936919979 6142
UVM_INFO @ 5072637712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 10426991366405023211664397939861627035261058292434491774856765764416501595168 3311
UVM_INFO @ 1785573845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98513871676907181636342805194395444043406959137246287666761509411414845403558 2339
UVM_INFO @ 1604281214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---