Simulation Results: lc_ctrl/volatile_unlock_enabled

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.36 %
  • code
  • 86.16 %
  • assert
  • 94.69 %
  • func
  • 96.24 %
  • line
  • 97.26 %
  • branch
  • 94.00 %
  • cond
  • 82.04 %
  • toggle
  • 88.33 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.260s 296.937us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.150s 61.292us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.220s 16.502us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.770s 64.093us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 141.956us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.660s 174.119us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.220s 16.502us 5 5 100.00
lc_ctrl_csr_aliasing 1.270s 141.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 8.780s 451.733us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 14.680s 398.868us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.180s 13.740us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.270s 258.376us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 12.420s 409.519us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 12.770s 3466.256us 19 20 95.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 12.420s 409.519us 20 20 100.00
lc_ctrl_prog_failure 3.270s 258.376us 20 20 100.00
lc_ctrl_errors 12.770s 3466.256us 19 20 95.00
lc_ctrl_security_escalation 7.860s 398.715us 20 20 100.00
lc_ctrl_jtag_state_failure 63.080s 18063.829us 20 20 100.00
lc_ctrl_jtag_prog_failure 14.090s 1062.740us 20 20 100.00
lc_ctrl_jtag_errors 41.740s 10828.599us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 7.170s 1484.773us 20 20 100.00
lc_ctrl_jtag_state_post_trans 14.480s 15441.425us 20 20 100.00
lc_ctrl_jtag_prog_failure 14.090s 1062.740us 20 20 100.00
lc_ctrl_jtag_errors 41.740s 10828.599us 20 20 100.00
lc_ctrl_jtag_access 13.560s 4936.573us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 23.500s 1392.709us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.340s 517.054us 10 10 100.00
lc_ctrl_jtag_csr_rw 1.980s 1805.468us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 21.820s 1856.602us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 4.310s 1057.075us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.830s 598.823us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.830s 197.459us 10 10 100.00
lc_ctrl_jtag_alert_test 1.950s 73.032us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 15.360s 7506.716us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.410s 30.164us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 383.270s 23052.512us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.490s 37.107us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.080s 481.789us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.080s 481.789us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.150s 61.292us 1 1 100.00
lc_ctrl_csr_rw 1.220s 16.502us 5 5 100.00
lc_ctrl_csr_aliasing 1.270s 141.956us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.560s 37.223us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.150s 61.292us 1 1 100.00
lc_ctrl_csr_rw 1.220s 16.502us 5 5 100.00
lc_ctrl_csr_aliasing 1.270s 141.956us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.560s 37.223us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.920s 1314.479us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 546.876us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 546.876us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 14.680s 398.868us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 12.420s 409.519us 20 20 100.00
lc_ctrl_sec_cm 9.920s 1314.479us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 12.420s 409.519us 20 20 100.00
lc_ctrl_sec_cm 9.920s 1314.479us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.420s 409.519us 20 20 100.00
lc_ctrl_sec_cm 9.920s 1314.479us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.420s 409.519us 20 20 100.00
lc_ctrl_sec_cm 9.920s 1314.479us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 12.420s 409.519us 20 20 100.00
lc_ctrl_sec_cm 9.920s 1314.479us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.420s 409.519us 20 20 100.00
lc_ctrl_sec_cm 9.920s 1314.479us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.420s 409.519us 20 20 100.00
lc_ctrl_sec_cm 9.920s 1314.479us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 12.420s 409.519us 20 20 100.00
lc_ctrl_sec_cm 9.920s 1314.479us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 7.860s 398.715us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 8.780s 451.733us 20 20 100.00
lc_ctrl_jtag_state_post_trans 14.480s 15441.425us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.970s 477.969us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.970s 477.969us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 7.750s 439.200us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 11.100s 3028.490us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 11.100s 3028.490us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
lc_ctrl_stress_all_with_rand_reset 86.160s 64722.753us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 41599763912760963578286863341777929329622713528755050333257027603271797232243 224
UVM_INFO @ 161185989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 25083091692974814202255461128778806327618232339625626970681844127043299009482 232
UVM_INFO @ 2735662949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 59929982556377179902031686557284988454605109815869505722405917435006071459587 1000
UVM_INFO @ 1440714159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50866316500742002833707323468983235744000119243696738590595545797289177617063 13631
UVM_INFO @ 19303604569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63595133218333868011605514653933911595319855145861643540665600841780960045676 3228
UVM_INFO @ 12087300695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70375943674943103027756008109379370421077183959438530140514244233302036394635 169
UVM_INFO @ 126559712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_errors 60998778858442173613905358365017595466068954324214983863410768442690341500115 2119
UVM_INFO @ 230693325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 78868737901140584306778573664938373634722573205265575567523747221005185068344 3651
UVM_INFO @ 27023942432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:933) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 63381613357941853541806545632633950592506625176386306017416714100754161446636 1533
UVM_INFO @ 1329668542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---