Simulation Results: otbn

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.67 %
  • code
  • 87.06 %
  • assert
  • 96.96 %
  • func
  • 100.00 %
  • block
  • 99.32 %
  • line
  • 99.52 %
  • branch
  • 95.03 %
  • toggle
  • 86.09 %
  • FSM
  • 67.61 %
Validation stages
V1
100.00%
V2
98.16%
V2S
97.57%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 15.000s 80.093us 1 1 100.00
otbn_smoke_vectorized 11.000s 114.136us 1 1 100.00
single_binary 100 100 100.00
otbn_single 39.000s 213.364us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 25.590us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 6.000s 20.794us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 12.000s 149.131us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 6.000s 43.259us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 11.000s 45.704us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 6.000s 20.794us 5 5 100.00
otbn_csr_aliasing 6.000s 43.259us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 156.000s 1547.105us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 45.000s 338.021us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 118.000s 572.796us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 97.000s 316.524us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 125.000s 910.309us 9 10 90.00
stress_all 10 10 100.00
otbn_stress_all 150.000s 268.220us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 37.000s 91.743us 60 60 100.00
zero_state_err_urnd 3 5 60.00
otbn_zero_state_err_urnd 10.000s 20.371us 3 5 60.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 29.000s 192.638us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 11.000s 20.726us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 7.000s 23.140us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 10.000s 101.554us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 10.000s 101.554us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 6.000s 25.590us 1 1 100.00
otbn_csr_rw 6.000s 20.794us 5 5 100.00
otbn_csr_aliasing 6.000s 43.259us 1 1 100.00
otbn_same_csr_outstanding 7.000s 97.897us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 6.000s 25.590us 1 1 100.00
otbn_csr_rw 6.000s 20.794us 5 5 100.00
otbn_csr_aliasing 6.000s 43.259us 1 1 100.00
otbn_same_csr_outstanding 7.000s 97.897us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 24 25 96.00
otbn_imem_err 20.000s 38.312us 9 10 90.00
otbn_dmem_err 21.000s 38.247us 15 15 100.00
internal_integrity 14 17 82.35
otbn_alu_bignum_mod_err 16.000s 227.199us 5 5 100.00
otbn_controller_ispr_rdata_err 18.000s 116.473us 4 5 80.00
otbn_mac_bignum_acc_err 28.000s 138.459us 4 5 80.00
otbn_urnd_err 9.000s 9.877us 1 2 50.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 11.000s 43.167us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 10.000s 19.907us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 11.000s 37.527us 10 10 100.00
tl_intg_err 30 30 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
otbn_tl_intg_err 93.000s 537.740us 25 25 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 68.000s 186.978us 4 5 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 80.093us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 21.000s 38.247us 15 15 100.00
sec_cm_instruction_mem_integrity 9 10 90.00
otbn_imem_err 20.000s 38.312us 9 10 90.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 93.000s 537.740us 25 25 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 37.000s 91.743us 60 60 100.00
sec_cm_controller_fsm_local_esc 37 40 92.50
otbn_imem_err 20.000s 38.312us 9 10 90.00
otbn_dmem_err 21.000s 38.247us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 20.371us 3 5 60.00
otbn_illegal_mem_acc 11.000s 43.167us 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 39.000s 213.364us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 37 40 92.50
otbn_imem_err 20.000s 38.312us 9 10 90.00
otbn_dmem_err 21.000s 38.247us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 20.371us 3 5 60.00
otbn_illegal_mem_acc 11.000s 43.167us 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 37.000s 91.743us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 37 40 92.50
otbn_imem_err 20.000s 38.312us 9 10 90.00
otbn_dmem_err 21.000s 38.247us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 20.371us 3 5 60.00
otbn_illegal_mem_acc 11.000s 43.167us 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 39.000s 213.364us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 18.000s 58.757us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 70.166us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 74.000s 177.630us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 74.000s 177.630us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 15.000s 37.223us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 40.000s 176.583us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 28.000s 252.311us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 28.000s 252.311us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 12.000s 30.291us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 39.000s 213.364us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 39.000s 213.364us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 39.000s 213.364us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 125.000s 910.309us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 39.000s 213.364us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 39.000s 213.364us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 36.000s 97.772us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 39.000s 213.364us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 624.000s 2214.291us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 551.000s 2108.977us 2 10 20.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 8 test runs
otbn_stress_all_with_rand_reset 79094002743324452216602532210184067086996437068572613683989393426843600402444 293
UVM_INFO @ 657653407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 6582491249950582305472255253241273455833471191316854648797358579838083957546 306
UVM_INFO @ 1657155560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 80407565145507905271199214321146524200673518302396309940222204233172423069409 228
UVM_INFO @ 7274027232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 64195068900061217236122208067073791448182579876642334113338358148500953773138 481
UVM_INFO @ 1866144516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 65913806745667766215013807787797113666496030494708870081575354545673104778311 169
UVM_INFO @ 569446003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 63900025088580238776634592539523275453732614867987065862871434955125367849689 193
UVM_INFO @ 204155806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 55552882668617342064625543871111143138737433785161460054551302168666175979448 235
UVM_INFO @ 354295845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 94654120563633286482708107679594365743296259377908448069529174764338470206785 178
UVM_INFO @ 870626329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 4 test runs
otbn_passthru_mem_tl_intg_err 100701646871041463438207588748784080346449839990824788247712759065457500204016 91
UVM_INFO @ 37462420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_multi 96412104817387209945081656705352826257625568653951872357959598364691450018330 162
UVM_INFO @ 52254624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_mac_bignum_acc_err 47104830606706148592217258493290937372902262859541572036905167047447761655122 107
UVM_INFO @ 71307586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 8640393035517947629711305808785657419012102538558394066176907117376057805256 110
UVM_INFO @ 3756371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_controller_ispr_rdata_err 36778794895664233117342333446816499587797029209879905867926375478448556347958 117
UVM_INFO @ 38948850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_imem_err 39582095826261425608859928448495822947506110892287416475366769098320620640968 111
UVM_INFO @ 38311665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_zero_state_err_urnd 29170512476847486571112116698388566453640527359326428452284196571836178418721 105
UVM_ERROR @ 64973916 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 64973916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 108514649894411640809315864314107299042790354300682587191614369623632445640170 109
UVM_ERROR @ 9876960 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 9876960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---