Simulation Results: otp_ctrl

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.18 %
  • code
  • 85.53 %
  • assert
  • 95.53 %
  • func
  • 92.48 %
  • line
  • 90.38 %
  • branch
  • 86.94 %
  • cond
  • 94.06 %
  • toggle
  • 92.90 %
  • FSM
  • 63.37 %
Validation stages
V1
92.31%
V2
95.35%
V2S
96.06%
V3
18.81%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.150s 78.065us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 13.160s 2411.747us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.330s 1447.015us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.310s 50.177us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.040s 1636.433us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.540s 52.451us 1 1 100.00
csr_mem_rw_with_rand_reset 3 5 60.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.540s 1092.564us 3 5 60.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.310s 50.177us 5 5 100.00
otp_ctrl_csr_aliasing 2.540s 52.451us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.620s 72.362us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.600s 45.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 18.100s 738.925us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 9.930s 2711.430us 300 300 100.00
partition_check 38 60 63.33
otp_ctrl_background_chks 63.030s 41031.419us 10 10 100.00
otp_ctrl_check_fail 77.900s 24895.893us 28 50 56.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 11.070s 416.180us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 73.690s 7148.721us 30 30 100.00
interface_key_check 9 10 90.00
otp_ctrl_parallel_key_req 19.530s 722.574us 9 10 90.00
lc_interactions 209 210 99.52
otp_ctrl_parallel_lc_req 23.150s 10832.898us 10 10 100.00
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
otp_dai_errors 23 25 92.00
otp_ctrl_dai_errs 53.100s 25966.564us 23 25 92.00
otp_macro_errors 7 10 70.00
otp_ctrl_macro_errs 34.610s 3110.902us 7 10 70.00
test_access 10 10 100.00
otp_ctrl_test_access 35.620s 7582.102us 10 10 100.00
stress_all 4 10 40.00
otp_ctrl_stress_all 243.440s 14985.141us 4 10 40.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.260s 597.056us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 3.690s 993.786us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 7.770s 193.703us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 7.770s 193.703us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 4.330s 1447.015us 1 1 100.00
otp_ctrl_csr_rw 2.310s 50.177us 5 5 100.00
otp_ctrl_csr_aliasing 2.540s 52.451us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.140s 159.459us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 4.330s 1447.015us 1 1 100.00
otp_ctrl_csr_rw 2.310s 50.177us 5 5 100.00
otp_ctrl_csr_aliasing 2.540s 52.451us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.140s 159.459us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
otp_ctrl_tl_intg_err 51.670s 19059.998us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 51.670s 19059.998us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 13.160s 2411.747us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 13.160s 2411.747us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_dai_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_lci_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
sec_cm_kdi_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
sec_cm_part_fsm_local_esc 206 210 98.10
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
otp_ctrl_macro_errs 34.610s 3110.902us 7 10 70.00
sec_cm_scrmbl_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
sec_cm_timer_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_dai_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_lci_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
sec_cm_kdi_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
sec_cm_part_fsm_global_esc 206 210 98.10
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
otp_ctrl_macro_errs 34.610s 3110.902us 7 10 70.00
sec_cm_scrmbl_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
sec_cm_timer_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 78.110s 10002.133us 199 200 99.50
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 9.930s 2711.430us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 28 50 56.00
otp_ctrl_check_fail 77.900s 24895.893us 28 50 56.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 73.690s 7148.721us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 73.690s 7148.721us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 73.690s 7148.721us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 73.690s 7148.721us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 73.690s 7148.721us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 13.160s 2411.747us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 73.690s 7148.721us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 13.160s 2411.747us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.560s 40400.711us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 11.070s 416.180us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 13.160s 2411.747us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 13.160s 2411.747us 10 10 100.00
sec_cm_macro_mem_integrity 7 10 70.00
otp_ctrl_macro_errs 34.610s 3110.902us 7 10 70.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 12.340s 8852.272us 1 1 100.00
stress_all_with_rand_reset 18 100 18.00
otp_ctrl_stress_all_with_rand_reset 3600.129s 0.000us 18 100 18.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 39 test runs
otp_ctrl_check_fail 47085778092521215203025701613076329214775242666046806482831048929872898297459 1015
UVM_INFO @ 118176021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 73914158721263810259946896721844231618574222348061476351410385366060911741935 13789
UVM_INFO @ 2995003146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 50501208094417783103176313585920642426923822583224422571116821068815223225289 1217
UVM_INFO @ 136375481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 44609533732471758601751679862506275486958030845274248547855503716387967902147 1894
UVM_INFO @ 466231952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 85338112457017334444954464380449313146914313750921670201927562889393577505153 13034
UVM_INFO @ 2849300757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 42869599179820093466679361571551444225667459869399948813065551191438030154684 113882
UVM_INFO @ 14985141102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 104086055893899330792910901154540465506236692910409166760349314717502181948090 3793
UVM_INFO @ 619370342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 78734869643635858883775023529752122509487994006996603672576731489815229085456 1899
UVM_INFO @ 1869260645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 5734768028822549477272671903403408187638488692539547499804023656450941825465 9826
UVM_INFO @ 388302113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 46303384326723848231930331260999524770797533062024003005348927359238156602269 6036
UVM_INFO @ 909580665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 68318904481707841276452228329990509114201887436763666865245810096164471223867 1185
UVM_INFO @ 188933501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 94575070131303470957971766727416260405257000696010263170744321514689805741579 2342
UVM_INFO @ 146634931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70180357961231543548281509414197310195070677078872525208935964991351587866987 5169
UVM_INFO @ 1799986760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 60080456397616060989599599938106164995366394581375837975364433682539656555254 2731
UVM_INFO @ 392695640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37841100347891331668670763522410533376746919000238944367134614955632194615533 5017
UVM_INFO @ 3436563899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 9231518765258279186013401461178442991130480899475982376445114003399244886410 2563
UVM_INFO @ 330836892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 67734529148231347058351379250671919498790649971519569024549063170936905778400 2629
UVM_INFO @ 130344213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 36902396750667863012091312531923457470045938590767209186557600122957167579073 6827
UVM_INFO @ 8275616342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 46593786928105342055889172581902250517970588657382352731782455092365185895788 155
UVM_INFO @ 563044364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 42668609670407158214023299220316673859308428459873405117637212294951910586924 1231
UVM_INFO @ 394202084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 87659157494459967025055339932307805642380766501905646818579547512558063828829 6061
UVM_INFO @ 10763162362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57354041707676686376939500237717693062991138453403336400908266280076801584107 5291
UVM_INFO @ 227803322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 45065917708680211117434356423658074994812409587897151447589811569511080844814 15233
UVM_INFO @ 1475562082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91396737907956636753180688881338654898197177951747589541727443923139761748921 151
UVM_INFO @ 95728192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 86604488354764825602616826505620310452847759873006976633656452153093139741968 597
UVM_INFO @ 40964980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44742699232603662506324692974683854418665141586628185280129178855112154472447 22890
UVM_INFO @ 3911673033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 100874387506782029904564045042715420787759061461648482946713144727538603807323 527
UVM_INFO @ 481225736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 17234433802031614294911299567021292006369712013329264827545147462830353948208 1443
UVM_INFO @ 301742386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 108383075108740348254784639030455643141782230697897980254583135299066334750092 10974
UVM_INFO @ 5613239656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 70095544854680432422396734631703924025909678202601173367828088785901317417483 1159
UVM_INFO @ 1805582485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 38271351591682408103093727140547157246575109427984634879400669229082773852798 2892
UVM_INFO @ 1130070006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 20361808127856009000941815338973124110569670973611389064455301486479162866635 4261
UVM_INFO @ 113890301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 23135943294203790995066491889212264471794535247851987900844797980623036961819 6840
UVM_INFO @ 1804446953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15658355242815878401883081592998343252136773390866706363558001264371700146568 3449
UVM_INFO @ 817096928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23243031595131298866807531114017628068521501770120129866598331731659699176737 153
UVM_INFO @ 141786507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48344540205384977994668174752385185058050717325718520093469040056704168027894 411
UVM_INFO @ 352758405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55395916367023723386969282236832968804647738811297241245033898902269501063789 4013
UVM_INFO @ 1664699041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73226831907843808686725807706218976367257673805256980417535056279943650689236 283
UVM_INFO @ 170415391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76159133691533363246528382307286352292145053010012731095446278409001974386871 27842
UVM_INFO @ 1924839919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 35 test runs
otp_ctrl_stress_all_with_rand_reset 67450121913506931455874483981935732856988273181441199962843806445689154206244 4342
UVM_INFO @ 945769490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88499637795534321115889881484409784547799135443160828493616542056588825141965 11587
UVM_INFO @ 4144776972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1381493672168170616623340614658437848063724393914380354464650992501628711707 2788
UVM_INFO @ 1874309907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82242478286013906056568760772634986700455680582322794991773632008570397253095 12640
UVM_INFO @ 27390959604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41162108508702782916845117027798909438077397913672802376915086908403217301694 2813
UVM_INFO @ 870723750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102524602392896614345219008129701466669496119834846756912570843678167990620131 7829
UVM_INFO @ 2703435859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56961189884782316285147564301133245153083077814330972785455433765446943239951 1831
UVM_INFO @ 1403715854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19935225044865907545929443506720242781681454689134113864064531934327778792665 34412
UVM_INFO @ 28224405150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 20337565309344103563458624060296734637367797789519545004710116194903909586660 17954
UVM_INFO @ 11631049717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44443542328247378444689291245158097328606515386974811730481526041209884466509 38518
UVM_INFO @ 12878818616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4543580466593836036637095399584355210390196066546636527687881191071904598955 11998
UVM_INFO @ 2146900045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109553583127317214383840620680471107547944197313134295704162502998625646464601 3162
UVM_INFO @ 2597526350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 108988473198603691385407732027267925534076526608086850058582674665311516084273 15514
UVM_INFO @ 7391131082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19119269328209883597612403177560065688862975339516775697566863751996594809539 1261
UVM_INFO @ 1012939975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11207848290394831035033272807157989229669174102157792645597521374233005910564 183
UVM_INFO @ 1145067193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24340193923820146611551526972556124403882652228189302843127969710457680303671 1906
UVM_INFO @ 4901782931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35175235994086872016181348055995841493635288382539495075179049614595905354588 441
UVM_INFO @ 1795062692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114159066385770498137254632581800951118063693376110404829394532040338226405025 16402
UVM_INFO @ 8269306694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29563725406198002971131500438348056634971995328860767633864534852760752803509 5008
UVM_INFO @ 802155307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105352457572047234491747303340964416723734794548722168837212977203905833197493 13134
UVM_INFO @ 1591050026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76142603461990416507522471765970498303703303174935466400178799354031778980310 8853
UVM_INFO @ 15393270248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103155591251163308651722126757823976857165713751811323989269321461445408033523 147
UVM_INFO @ 34551231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95695492555755875492235542266274804842961092276195619205217884486893196063201 9789
UVM_INFO @ 16990788938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80216333857000843467747337202522785098382433419995505349956654752018220495015 155
UVM_INFO @ 39956998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61783362799440735757160474799966774350124636235782783887824930044265070113580 25883
UVM_INFO @ 25582352786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69244294442828179237799431630539863299739884687575005015566532785565535133375 3248
UVM_INFO @ 16841343720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11547896998292314229058951018647779488162025912118488213020135923775683938339 9016
UVM_INFO @ 2874020206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84496223943626795026829997059274666380911055716573663140488054685012984917782 10440
UVM_INFO @ 53407668511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18101269458149813995481087379886377722465859384052172212361454647016050344616 503
UVM_INFO @ 851416167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44400248623079757269361953910791645816052021319713044278204385749281739796862 6118
UVM_INFO @ 15324595430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68938376200507481131678013526903390084034878330882307220343428442747913489393 5446
UVM_INFO @ 979389675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85522291166524425175148817164451825538282642386783327052049666341533223647769 1616
UVM_INFO @ 3672864018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101595902719366428802587454704473119013523032292730612759003296118112291340918 7173
UVM_INFO @ 1317952906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21058608997142438229337688809417387183584813105730693871610583455363344111005 320
UVM_INFO @ 2159848624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96412849416622316502619519896296049424851865375857929053129934661784991279023 5660
UVM_INFO @ 3551152511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1824) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 23 test runs
otp_ctrl_stress_all_with_rand_reset 60621578329680270674155467985770206645267875249881467095166928793442660897478 3324
UVM_INFO @ 172410197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97293813445207529897018201700300958235088175064939722937699352645294136833271 99
UVM_INFO @ 55270918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75523625410719354053379075380343318383960832758173176266782853422764383552392 6737
UVM_INFO @ 1207616499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81495320704405656477925761136307575004308119440295879135906038098887855461616 27093
UVM_INFO @ 15584345991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85929872383580982733751536918767801457149591414053334810558904151750665722841 6562
UVM_INFO @ 3467313448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 108320809685911391399768348295065929720586192977053825644347008299366549243970 5780
UVM_INFO @ 1211135633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42469721599143107138890484461023939605748992016541133138617556045336027804117 98
UVM_INFO @ 28608859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72164558789850067562788830840355910072023029203124124188226020310540058694491 27405
UVM_INFO @ 1633563775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18524883898889098378275509461438934235726759580727729991533069474822003040288 152
UVM_INFO @ 84089282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 31843270246988424764598356113200647194314771942828673055980547055677564119245 98
UVM_INFO @ 70726506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 115428356706761775840219713217436924069056696296195067551562203912177617378418 13803
UVM_INFO @ 1689124771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87026664664956334715004429562603357416586873586509766522746802415408634226074 98
UVM_INFO @ 53642510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 115403918031826707618470912418243646654011951005234397967170797737764469143671 5644
UVM_INFO @ 3946153001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42790932902373611530529722558565059401987718704758380561633701215860067032860 14892
UVM_INFO @ 1696427180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77017075224175407386937077256612024747033069529219973916086768669279430434091 1488
UVM_INFO @ 160281266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12465572519546196462483186538057662467184864954935787965376749572489755202742 98
UVM_INFO @ 106739929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76647306722570171561568916336380591044238055536129824782860648324451930024180 99
UVM_INFO @ 432922219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70522656642473750876841688618912051876094324226534518338423276849464548890703 99
UVM_INFO @ 26348160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71433334735701062507452518298783887988275756465746279082219259587512263509340 26296
UVM_INFO @ 3529130444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51085979426362086434681807026722006469393805850642405362058548770282030120251 9274
UVM_INFO @ 1685086837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114442361762367160690989574631772827617506963920221343315853404608477878431994 98
UVM_INFO @ 92950948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79256534231939351170208007926712897319277125326196108513346010801098732914687 13437
UVM_INFO @ 3248152968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86047783204343210007292757502311656481600098284950535821917343949676024291952 98
UVM_INFO @ 107848752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:764) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 9 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 30419427252154207342806494958000291123127179582743307320698389147473902444324 98
UVM_INFO @ 109433780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 85228855115666374795297066475667531883466408130668930845043899645950170958987 104
UVM_INFO @ 63948207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89420656091974698614324662803282996137982661144480404714620307755283459475433 13662
UVM_INFO @ 15404739083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63653563071354034592161252808442847545080022732457878470591992876587551516151 98
UVM_INFO @ 47283880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56284378786585541970613156575530579171627142293165437611692425154780359022221 7340
UVM_INFO @ 1819267809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15177137920616950492480869507520073269748144903886410822692030967292485931746 23343
UVM_INFO @ 2266118836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39565360118318800027506896526426682051246214803735130362959922870218085351250 98
UVM_INFO @ 28123106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89735280572916993656018119408930120138967852206412728296039953798000421926029 4036
UVM_INFO @ 818445922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112262813004875146212272636996345317033046946253572934607771353566342164626685 10397
UVM_INFO @ 1786209634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles 7 test runs
otp_ctrl_stress_all_with_rand_reset 74303726614347299799225401000144436123491550200009446391014835247364581644696 1000
UVM_INFO @ 6497046260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 63108485476273642277670579457208098135685636486580676770732533873717836104901 26880
UVM_INFO @ 539545946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 62325608966543551160807884128535344491986529720525430446162962789481194023795 2600
UVM_INFO @ 336695562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 962543142951468283312541525472058024572019180315086243386065135869102689643 91623
UVM_INFO @ 13243166388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 99265321696055081359262377637691450716945325918351086613456539697016499408456 87425
UVM_INFO @ 30692860881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 105033855781689925746728446965082945640341750094260202046707341490821105379151 45236
UVM_INFO @ 65110737204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 49927588232063262192691725649728929140062625400589919615407125572176689330651 2300
UVM_INFO @ 685213024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 2 test runs
otp_ctrl_stress_all_with_rand_reset 78046283593717110075702899508937176587481468297732396685823412756762507640884 8351
UVM_ERROR @ 730833528 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 730833528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91131681528341852013849287428025156267079506887306341092601547939840172478493 31621
UVM_ERROR @ 70336960703 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 70336960703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:283) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 98578357195003462264006252885069353018121345598183395335412764944974843377218 19970
UVM_INFO @ 10861090112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 1 test run
otp_ctrl_stress_all_with_rand_reset 83421500591988403083284153259654429209668450556803418785138954149510013301574 4930
UVM_INFO @ 3594971572 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 3595054906 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 3596179915 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 3596304916 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
Job timed out after * minutes 1 test run
otp_ctrl_stress_all_with_rand_reset 55546758746320978511002861513612058723348439595125457779144049415848676861597 None
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_parallel_lc_esc_vseq] wait timeout occurred! 1 test run
otp_ctrl_parallel_lc_esc 1050679532852079053749961332189973363840531815379212326386127196831433634319 95
UVM_INFO @ 10002133269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---