Simulation Results: pwrmgr

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.94 %
  • code
  • 95.01 %
  • assert
  • 97.13 %
  • func
  • 98.68 %
  • line
  • 99.09 %
  • branch
  • 96.19 %
  • cond
  • 95.76 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
95.65%
V2
89.78%
V2S
70.43%
V3
35.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 1.000s 24.731us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.950s 66.371us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.950s 21.607us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 3.920s 1710.175us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.020s 23.571us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
pwrmgr_csr_mem_rw_with_rand_reset 3600.038s 0.000us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.950s 21.607us 5 5 100.00
pwrmgr_csr_aliasing 1.020s 23.571us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.430s 314.865us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.430s 314.865us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.400s 46.514us 10 10 100.00
pwrmgr_lowpower_invalid 1.030s 44.749us 10 10 100.00
reset 16 20 80.00
pwrmgr_reset 3.700s 1000.000us 8 10 80.00
pwrmgr_reset_invalid 3600.053s 0.000us 8 10 80.00
main_power_glitch_reset 8 10 80.00
pwrmgr_reset 3.700s 1000.000us 8 10 80.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.950s 332.063us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.710s 268.077us 10 10 100.00
disable_rom_integrity_check 9 10 90.00
pwrmgr_disable_rom_integrity_check 2.360s 1000.000us 9 10 90.00
stress_all 1 10 10.00
pwrmgr_stress_all 10800.055s 0.000us 1 10 10.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.950s 18.103us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.810s 120.883us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.810s 120.883us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.950s 66.371us 1 1 100.00
pwrmgr_csr_rw 0.950s 21.607us 5 5 100.00
pwrmgr_csr_aliasing 1.020s 23.571us 1 1 100.00
pwrmgr_same_csr_outstanding 1.270s 153.947us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.950s 66.371us 1 1 100.00
pwrmgr_csr_rw 0.950s 21.607us 5 5 100.00
pwrmgr_csr_aliasing 1.020s 23.571us 1 1 100.00
pwrmgr_same_csr_outstanding 1.270s 153.947us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 6 30 20.00
pwrmgr_tl_intg_err 3600.048s 0.000us 6 25 24.00
pwrmgr_sec_cm 3600.044s 0.000us 0 5 0.00
prim_count_check 0 5 0.00
pwrmgr_sec_cm 3600.044s 0.000us 0 5 0.00
prim_fsm_check 0 5 0.00
pwrmgr_sec_cm 3600.044s 0.000us 0 5 0.00
sec_cm_bus_integrity 6 25 24.00
pwrmgr_tl_intg_err 3600.048s 0.000us 6 25 24.00
sec_cm_lc_ctrl_intersig_mubi 9 10 90.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.020s 700.299us 9 10 90.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.950s 332.063us 10 10 100.00
pwrmgr_repeat_wakeup_reset 3.350s 857.109us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.240s 201.355us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.930s 32.289us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 0 5 0.00
pwrmgr_sec_cm 3600.044s 0.000us 0 5 0.00
sec_cm_fsm_sparse 0 5 0.00
pwrmgr_sec_cm 3600.044s 0.000us 0 5 0.00
sec_cm_fsm_terminal 0 5 0.00
pwrmgr_sec_cm 3600.044s 0.000us 0 5 0.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.960s 39.869us 10 10 100.00
sec_cm_main_pd_rst_local_esc 1 10 10.00
pwrmgr_glitch 3600.053s 0.000us 1 10 10.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.750s 273.334us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.950s 21.607us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.950s 21.607us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 6 10 60.00
pwrmgr_escalation_timeout 1.260s 105.903us 6 10 60.00
stress_all_with_rand_reset 1 10 10.00
pwrmgr_stress_all_with_rand_reset 3600.043s 0.000us 1 10 10.00

Error Messages

   Test seed line log context
Job timed out after * minutes 48 test runs
pwrmgr_glitch 39250507556315258946256027526026271952982880854887676551893055375538650748472 None
pwrmgr_tl_intg_err 102999969304586448540317153578623914575107429808549130955389201495753936743752 None
pwrmgr_sec_cm 13408007078070551506470501116477591241557644872838480030528336185694995503472 None
pwrmgr_stress_all_with_rand_reset 92018376371438646721209994959121044719650806589159450720487058309671303297131 None
pwrmgr_glitch 49745909255256809177184855128788968033494295885625498057109424268908984047291 None
pwrmgr_sec_cm 37974135371927405647969266245475424193345262719412315936934010028725688599766 None
pwrmgr_stress_all_with_rand_reset 66184354388208743723952106209909803063820215070946268279261233703851921142961 None
pwrmgr_stress_all 105433604432956806582477767155057629668908938940032207905365548468223328284617 None
pwrmgr_glitch 29802607434019312751703405821393130112330978165701230736168869058166866534923 None
pwrmgr_tl_intg_err 110036576744709257177667575515155937873605047810334595966552317316244470739521 None
pwrmgr_sec_cm 33749162257217176648587496519287984319171806811581720571614597132456387700118 None
pwrmgr_stress_all_with_rand_reset 85283962155227251375791185835604063267920486836954776913731702479176574737853 None
pwrmgr_glitch 88856192815211182931222971875910955887802797514592541794003755248379085857838 None
pwrmgr_tl_intg_err 24654330823447302029445629386216774318116126022035231905243314428136045610191 None
pwrmgr_sec_cm 17850645851668218257817457702900007784440772302581790111393500737090039419269 None
pwrmgr_stress_all_with_rand_reset 53621486769230887854319248220488037675040010882967016209568465135252215556403 None
pwrmgr_glitch 21847100208172816283546449679954850108135149748161115781013338430841185881090 None
pwrmgr_tl_intg_err 77145699120528504370680996631611816682835633569373604344262939693106624225898 None
pwrmgr_sec_cm 81886025916692052471025453097018524014027235047738581749173188140460099533216 None
pwrmgr_csr_mem_rw_with_rand_reset 47409482708687376446798362718896799060021284471653666432552228412738631916181 None
pwrmgr_glitch 39553064133346467662140037811020490701181024388321203126235695030397081083280 None
pwrmgr_tl_intg_err 4257593604844225146633201616302209220523123697461303511877298079455485832902 None
pwrmgr_stress_all_with_rand_reset 495258128639528041931854633760977598379041469898680403028560453288145556512 None
pwrmgr_tl_intg_err 49587110372769670446839524322994016582966419538269108959704249728810538835845 None
pwrmgr_stress_all_with_rand_reset 93506553205330359348654863584179617104758657135129042789714425562066553261838 None
pwrmgr_stress_all 55793840471092340275051696229980200178289444636237445712269861004689542712041 None
pwrmgr_glitch 10434386971546651165085656703852966448633446772912632165432593128360756733159 None
pwrmgr_reset_invalid 5451303573974552299938430214967373348908421641932148285434301693913329892958 None
pwrmgr_tl_intg_err 101641943238708432281446382386571776288869368011378702046488273325195962950093 None
pwrmgr_stress_all_with_rand_reset 30438645336844119953074659361911958395427296607363384770454277871006753357741 None
pwrmgr_glitch 64489110268625019580050479930041112924688403673163878757765885600059193364942 None
pwrmgr_tl_intg_err 87156172385406926499798890349574994352699707754170020534865082950147839262290 None
pwrmgr_stress_all_with_rand_reset 23311566369497535757643436809917873496708859300003084234944823399784551822922 None
pwrmgr_stress_all 112392182656546812171182655422375928451314010750144020496361299539221992357276 None
pwrmgr_glitch 94778968961924084215478582415076018619166621776011360856710003443113834983450 None
pwrmgr_tl_intg_err 162658687725565461390304844353228629910567211746685653494169949751057741558 None
pwrmgr_stress_all_with_rand_reset 98514674600568925917554103083755246209617961501215816525577868260760309176116 None
pwrmgr_stress_all 22280901882225745464708151557054404904752168201080710316240595728982184045308 None
pwrmgr_tl_intg_err 21017330166044290623362682534585581411881454212522528389910754480273448637784 None
pwrmgr_tl_intg_err 100343195616776664235330374998172661740639973049981027178525594940776802268210 None
pwrmgr_tl_intg_err 95976293308823423407501659952466478705550207855987450976088234323450271211833 None
pwrmgr_tl_intg_err 9754507837785734396092681511742823430387736747113874812412732786428357418845 None
pwrmgr_tl_intg_err 91831388937359592721277380839370710473035725586710994304714285156595207780549 None
pwrmgr_tl_intg_err 5989060750299277117986458593660920593334252126938823020279641759797251633592 None
pwrmgr_tl_intg_err 50075135947177370585883736322964660201491649682000354785163074587064442152982 None
pwrmgr_tl_intg_err 87503200317835760816520404673970792547796576002862767704816927957551427181737 None
pwrmgr_tl_intg_err 61712957848729259373146681144492576586365980515887665565999806759470555380538 None
pwrmgr_tl_intg_err 103473068259123267260764757995597910255888214825296608357786421381661004495345 None
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 5 test runs
pwrmgr_stress_all 111247292828199664817613556034670803772552189501573394645945698068698821453340 361
UVM_INFO @ 10325268080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 88496695241761697344557968229247473504968258687323215919328289728370471983601 722
UVM_INFO @ 12367234114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 41757805727238290500669814850093011249833601337177322766628992934576062414458 552
UVM_INFO @ 11532313737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 76310695135109989055018562072400672020176545043759815821307200159037726409178 215
UVM_INFO @ 10200790978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 83946756986296142553275987281490475316882254350496211084932140956119365568891 366
UVM_INFO @ 10567647534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
pwrmgr_reset 68919157008500934193318070290957448958531738506197030011216680878940938697589 121
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 92394098726400746504135550743891991293036078699705630498687521769138742035223 110
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 114319322772276395631990613242773150032251604232137913973796492704531819863764 431
UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 11020419653953534704552329440724062951730686875909218817870513627201990802757 105
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 4 test runs
pwrmgr_escalation_timeout 14382328240728773432282182550128589754216484200318553106015334519391921958083 85
UVM_ERROR @ 968544477 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 968544477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 52896394388772265096264451086299726433470335323467042054320730275079398322316 85
UVM_ERROR @ 370441078 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 370441078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 95879860134775141657358259355724134524556446104974037083166770757536236597383 85
UVM_ERROR @ 356879076 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 356879076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 44822626172733604424513803302937317945495739630314205687629243656605040346873 85
UVM_ERROR @ 369457832 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 369457832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitRomCheck 1 test run
pwrmgr_reset_invalid 48665809305153286385318503460712505546271459486587184892585702534260443664526 97
UVM_INFO @ 170067655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---