Simulation Results: rom_ctrl/192kb

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.05 %
  • code
  • 97.19 %
  • assert
  • 97.68 %
  • func
  • 99.28 %
  • line
  • 99.21 %
  • branch
  • 99.28 %
  • cond
  • 98.81 %
  • toggle
  • 95.34 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 29.470s 1072.795us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 46.040s 57.759us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 18.500s 57.013us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 14.700s 122.597us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 17.070s 75.284us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 18.650s 60.543us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 18.500s 57.013us 5 5 100.00
rom_ctrl_csr_aliasing 17.070s 75.284us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 14.860s 49.447us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 19.000s 52.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 29.510s 4266.473us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 114.890s 4059.079us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 29.980s 76.552us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 19.230s 52.702us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 35.770s 1373.985us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 35.770s 1373.985us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 46.040s 57.759us 1 1 100.00
rom_ctrl_csr_rw 18.500s 57.013us 5 5 100.00
rom_ctrl_csr_aliasing 17.070s 75.284us 1 1 100.00
rom_ctrl_same_csr_outstanding 33.390s 164.170us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 46.040s 57.759us 1 1 100.00
rom_ctrl_csr_rw 18.500s 57.013us 5 5 100.00
rom_ctrl_csr_aliasing 17.070s 75.284us 1 1 100.00
rom_ctrl_same_csr_outstanding 33.390s 164.170us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 785.200s 34146.466us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 147.380s 5961.117us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 2504.940s 762.293us 5 5 100.00
rom_ctrl_tl_intg_err 637.070s 675.035us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 2504.940s 762.293us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 2504.940s 762.293us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 785.200s 34146.466us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 785.200s 34146.466us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 785.200s 34146.466us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 785.200s 34146.466us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 785.200s 34146.466us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 2504.940s 762.293us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 2504.940s 762.293us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 29.470s 1072.795us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 29.470s 1072.795us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 29.470s 1072.795us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 637.070s 675.035us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 785.200s 34146.466us 20 20 100.00
rom_ctrl_kmac_err_chk 29.980s 76.552us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 785.200s 34146.466us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 785.200s 34146.466us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 785.200s 34146.466us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 147.380s 5961.117us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 2504.940s 762.293us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 370.060s 14686.934us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 42900866804718564536275987598891903911040045457197082302164237318163094867685 85
UVM_INFO @ 2049951695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 64048563778110557687810320926026419506400206358881579093459563740019673333869 85
UVM_INFO @ 4266472587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---