| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| rstmgr_smoke | 2.180s | 267.706us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.240s | 107.158us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.140s | 87.568us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rstmgr_csr_bit_bash | 9.890s | 2456.767us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rstmgr_csr_aliasing | 1.320s | 100.035us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rstmgr_csr_mem_rw_with_rand_reset | 1.650s | 196.153us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rstmgr_csr_rw | 1.140s | 87.568us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 1.320s | 100.035us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_stretcher | 5 | 5 | 100.00 | |||
| rstmgr_por_stretcher | 1.370s | 146.822us | 5 | 5 | 100.00 | |
| sw_rst | 5 | 5 | 100.00 | |||
| rstmgr_sw_rst | 2.810s | 415.534us | 5 | 5 | 100.00 | |
| sw_rst_reset_race | 5 | 5 | 100.00 | |||
| rstmgr_sw_rst_reset_race | 1.890s | 255.872us | 5 | 5 | 100.00 | |
| reset_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 10.710s | 2318.221us | 5 | 5 | 100.00 | |
| cpu_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 10.710s | 2318.221us | 5 | 5 | 100.00 | |
| alert_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 10.710s | 2318.221us | 5 | 5 | 100.00 | |
| reset_info_capture | 5 | 5 | 100.00 | |||
| rstmgr_reset | 10.710s | 2318.221us | 5 | 5 | 100.00 | |
| stress_all | 5 | 5 | 100.00 | |||
| rstmgr_stress_all | 62.870s | 20015.407us | 5 | 5 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rstmgr_alert_test | 1.200s | 102.356us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rstmgr_tl_errors | 4.570s | 547.486us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rstmgr_tl_errors | 4.570s | 547.486us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.240s | 107.158us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 1.140s | 87.568us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 1.320s | 100.035us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 2.230s | 253.703us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.240s | 107.158us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 1.140s | 87.568us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 1.320s | 100.035us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 2.230s | 253.703us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rstmgr_sec_cm | 41.770s | 16828.789us | 5 | 5 | 100.00 | |
| rstmgr_tl_intg_err | 4.330s | 944.582us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 41.770s | 16828.789us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 41.770s | 16828.789us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rstmgr_tl_intg_err | 4.330s | 944.582us | 25 | 25 | 100.00 | |
| sec_cm_scan_intersig_mubi | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm_scan_intersig_mubi | 1.700s | 201.367us | 5 | 5 | 100.00 | |
| sec_cm_leaf_rst_bkgn_chk | 25 | 25 | 100.00 | |||
| rstmgr_leaf_rst_cnsty | 11.510s | 2573.254us | 25 | 25 | 100.00 | |
| sec_cm_leaf_rst_shadow | 5 | 5 | 100.00 | |||
| rstmgr_leaf_rst_shadow_attack | 1.850s | 301.616us | 5 | 5 | 100.00 | |
| sec_cm_leaf_fsm_sparse | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 41.770s | 16828.789us | 5 | 5 | 100.00 | |
| sec_cm_sw_rst_config_regwen | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.140s | 87.568us | 5 | 5 | 100.00 | |
| sec_cm_dump_ctrl_config_regwen | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.140s | 87.568us | 5 | 5 | 100.00 | |