Simulation Results: rv_timer

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.69 %
  • code
  • 94.66 %
  • assert
  • 98.41 %
  • func
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 1.950s 166.714us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.750s 25.223us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 0.900s 56.686us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.670s 892.743us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.930s 13.961us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.990s 153.984us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 0.900s 56.686us 5 5 100.00
rv_timer_csr_aliasing 0.930s 13.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 20 20 100.00
rv_timer_random_reset 22.850s 30697.958us 20 20 100.00
disabled 20 20 100.00
rv_timer_disabled 4.420s 2693.323us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 534.620s 419155.733us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 534.620s 419155.733us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 5.920s 3107.427us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 0.860s 14.680us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 0.870s 19.468us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.260s 191.446us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.260s 191.446us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 0.750s 25.223us 1 1 100.00
rv_timer_csr_rw 0.900s 56.686us 5 5 100.00
rv_timer_csr_aliasing 0.930s 13.961us 1 1 100.00
rv_timer_same_csr_outstanding 1.130s 140.073us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 0.750s 25.223us 1 1 100.00
rv_timer_csr_rw 0.900s 56.686us 5 5 100.00
rv_timer_csr_aliasing 0.930s 13.961us 1 1 100.00
rv_timer_same_csr_outstanding 1.130s 140.073us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.300s 384.480us 5 5 100.00
rv_timer_tl_intg_err 1.710s 122.471us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 1.710s 122.471us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 3 10 30.00
rv_timer_min 1.280s 63.769us 3 10 30.00
max_value 1 10 10.00
rv_timer_max 1.080s 87.051us 1 10 10.00
stress_all_with_rand_reset 20 20 100.00
rv_timer_stress_all_with_rand_reset 59.650s 41793.860us 20 20 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 7 test runs
rv_timer_min 52373871169256214263394675025127719044063574830696228757649026277233326860352 81
UVM_INFO @ 211991489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 50077437527258558864547562312489922846800774279728096175930486867352163240075 81
UVM_INFO @ 63768902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 61293457959736205531427186535120760157201422990571173362477599130286943771675 83
UVM_INFO @ 59373816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 19781186115856698447069601738217584606405015485838874660720499945364593407509 82
UVM_INFO @ 56419840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 77597058287681819560389238771578906075147422405131149892923484905783920412421 83
UVM_INFO @ 137399221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 104666312002726149384937320335957628050218608033353476739864111168998260133993 85
UVM_INFO @ 63598620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 63272289467297565878114138626623568696890122174101088243388765589983635353884 82
UVM_INFO @ 87636496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 7 test runs
rv_timer_max 57747426240520261081846731429008852886700548255021086660651784364489834293072 81
UVM_INFO @ 43476768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 110136202125121178419648248552881835207191510031410827217486096508450080912257 81
UVM_INFO @ 265116604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 80171276250886023064363420456419485758453959976604119020256369606963003191898 81
UVM_INFO @ 88131088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 21680799593813868121617273754336119450137689589190414140618775743240717528288 81
UVM_INFO @ 50599526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 29135366299702569782516167527942016585602471111809362982209068466707401392947 81
UVM_INFO @ 86280509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 48025642777591447906791499164980958720038128157479542632575696417326762693920 81
UVM_INFO @ 47341867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 16276760116589536913876308625273776900101165166816689688819663564358111274378 81
UVM_INFO @ 46235493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:342) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 2 test runs
rv_timer_max 189109037909828070460422954352798031325257892686839852247524180921265886088 81
UVM_INFO @ 79942763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 75508620393138661247412489057900121306516575060638910766052139192840002684552 81
UVM_INFO @ 87050995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---