Simulation Results: spi_host

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.88 %
  • code
  • 91.30 %
  • assert
  • 96.60 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.90%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 92.000s 2749.221us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 57.646us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 59.162us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 793.766us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 28.438us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 59.748us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 59.162us 5 5 100.00
spi_host_csr_aliasing 1.000s 28.438us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 14.958us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 65.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 28.899us 10 10 100.00
error_event_intr 29 30 96.67
spi_host_overflow_underflow 4.000s 150.070us 10 10 100.00
spi_host_error_cmd 2.000s 39.235us 10 10 100.00
spi_host_event 669.000s 96786.339us 9 10 90.00
clock_rate 10 10 100.00
spi_host_speed 13.000s 796.147us 10 10 100.00
speed 10 10 100.00
spi_host_speed 13.000s 796.147us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 13.000s 796.147us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 764.000s 63595.494us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 22.000s 61.324us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 60.766us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 13.000s 796.147us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 13.000s 796.147us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 92.000s 2749.221us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 92.000s 2749.221us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 73.000s 11609.706us 10 10 100.00
spien 10 10 100.00
spi_host_spien 13.000s 725.833us 10 10 100.00
stall 9 10 90.00
spi_host_status_stall 2994.000s 1000000.000us 9 10 90.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 4.000s 120.439us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 4.000s 150.070us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 9.000s 15.619us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 18.824us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 21.000s 140.943us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 21.000s 140.943us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 57.646us 1 1 100.00
spi_host_csr_rw 2.000s 59.162us 5 5 100.00
spi_host_csr_aliasing 1.000s 28.438us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 28.439us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 57.646us 1 1 100.00
spi_host_csr_rw 2.000s 59.162us 5 5 100.00
spi_host_csr_aliasing 1.000s 28.438us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 28.439us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 20.000s 61.656us 25 25 100.00
spi_host_sec_cm 2.000s 76.209us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 20.000s 61.656us 25 25 100.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_host_event_vseq.sv:45) [spi_host_event_vseq] Check failed txqd == spi_host_ctrl_reg.tx_watermark - i (* [*] vs * [*]) 1 test run
spi_host_event 113578232858148730784977509045697189574328085886430156168337519757476682226155 101
UVM_INFO @ 95106232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_status_stall 76344141679258954080767839624865119687293652837040736160877955211737515515360 14677
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---