| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 3032.194us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 40.392us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 12.738us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 2.000s | 383.296us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 1.000s | 12.159us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 6.000s | 1406.547us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 12.738us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 12.159us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 354.000s | 44451.682us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 174.000s | 10373.323us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 57.000s | 24398.817us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 325.000s | 13995.847us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 285.000s | 218609.266us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 128.000s | 214017.947us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 64.000s | 16368.465us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 73.000s | 10010.002us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 8.000s | 7448.170us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 530.000s | 100861.057us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 7.000s | 2777.032us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 7.000s | 2776.657us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 7.000s | 6696.484us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 19.000s | 1302.753us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 4.000s | 724.117us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 3032.194us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 8.000s | 7448.170us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 128.000s | 214017.947us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 632.000s | 95468.328us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 4.000s | 22.899us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 8.000s | 617.331us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 8.000s | 617.331us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 40.392us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 12.738us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 12.159us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 30.580us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 40.392us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 12.738us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 12.159us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 30.580us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 38.000s | 7465.785us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.017us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 1697.170us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.017us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 1697.170us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 19.000s | 1302.753us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 19.000s | 1302.753us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 12.738us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 73.000s | 10010.002us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 73.000s | 10010.002us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 73.000s | 10010.002us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 64.000s | 16368.465us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3602.057s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 38.000s | 7465.785us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 3032.194us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 3032.194us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 73.000s | 10010.002us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.017us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 64.000s | 16368.465us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.017us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.017us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 3032.194us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.017us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 80.000s | 12582.937us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 84205024731075032663363694744621037425617419863571749072863650399589461509798 | None | ||
| sram_ctrl_mubi_enc_err | 100320598623323483363425760342941835778004259468956254418932956102724322723589 | None | ||
| sram_ctrl_readback_err | 40864559820638536349382578450550890658270649109808832829014243513566192726955 | None | ||
| sram_ctrl_mubi_enc_err | 109549353296620139827939726980219928751252484799252587985897357572451726131354 | None | ||
| sram_ctrl_readback_err | 86026776889533669154195992673507956271121714205484377602270125656310540989396 | None | ||
| sram_ctrl_mubi_enc_err | 6742487166917911484315401129956060401861827029276738107597327227557937286021 | None | ||
| sram_ctrl_readback_err | 448409213059402042698270148866816869054065686647795237627341582761269273231 | None | ||
| sram_ctrl_mubi_enc_err | 85381897417148198049503182903989812029395649969533592629826685965532423018401 | None | ||
| sram_ctrl_readback_err | 91473370171415796660798305178474303905134308674153477752064161434570008840591 | None | ||
| sram_ctrl_mubi_enc_err | 100033316183169179966560230694692357308453839709460051707378415119010401742107 | None | ||
| sram_ctrl_readback_err | 3809044066971793455374057914435989066070347994562501079278855589268735217775 | None | ||
| sram_ctrl_mubi_enc_err | 15043752977803943168779796064294831752211694495244132696355637640872909036732 | None | ||
| sram_ctrl_readback_err | 59578247345681111361393379507379761668724777964517405572278346742050252655741 | None | ||
| sram_ctrl_mubi_enc_err | 67167704704170467221294757827347053375894492264132375818260973480238579022823 | None | ||
| sram_ctrl_readback_err | 98433660732879989905099727084268096591562635061256962155935643984800728298973 | None | ||
| sram_ctrl_mubi_enc_err | 75936003027709372710051541959320764256517196782375887656071919279593173888929 | None | ||