| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 270.251us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 15.149us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 15.211us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 2.000s | 741.821us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 1.000s | 26.171us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 2.000s | 36.973us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 15.211us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 26.171us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 14.000s | 3380.635us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 7.000s | 684.654us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 30.000s | 175.337us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 279.000s | 16377.107us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 10.000s | 2299.178us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 20.000s | 4132.087us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 7.000s | 1733.916us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 9216.220us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 3.000s | 79.605us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 500.000s | 25522.571us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 39.954us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 2.000s | 68.909us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 3.000s | 43.917us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 16.000s | 1579.327us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 47.096us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 270.251us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 3.000s | 79.605us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 20.000s | 4132.087us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 90.000s | 42749.155us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 27.494us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 161.659us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 161.659us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 15.149us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 15.211us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 26.171us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 238.239us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 15.149us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 15.211us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 26.171us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 238.239us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 740.243us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 860.402us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 580.591us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 860.402us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 580.591us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 16.000s | 1579.327us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 16.000s | 1579.327us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 15.211us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 9216.220us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 9216.220us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 9216.220us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 7.000s | 1733.916us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3600.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 740.243us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 270.251us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 270.251us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 9216.220us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 860.402us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 7.000s | 1733.916us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 860.402us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 860.402us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 270.251us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 860.402us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 69.000s | 2674.322us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 32247795170861857652018545605081598037230792351465458183005380013994306391899 | None | ||
| sram_ctrl_mubi_enc_err | 8440568065899052202420318244378616874380285008555220572978916913246882908574 | None | ||
| sram_ctrl_readback_err | 79377702370407878122189849962682839733217247684238375833174509884137794417131 | None | ||
| sram_ctrl_mubi_enc_err | 38944947905820128578492147484017562978266045292066645675468966594602725504163 | None | ||
| sram_ctrl_readback_err | 76329858097245875442445447360541547362976407946771635301533571958398829087464 | None | ||
| sram_ctrl_mubi_enc_err | 77883191049855467021134884068770761094878071139150107954380955164702220230277 | None | ||
| sram_ctrl_readback_err | 101697244257977280051268466624409964196611037953357280642114008501131318895315 | None | ||
| sram_ctrl_mubi_enc_err | 57576147309962963349259071403642594937057114469552543948431500999240432822541 | None | ||
| sram_ctrl_readback_err | 55514928223609171793927781129290800273955803519568876160188135501280408459226 | None | ||
| sram_ctrl_mubi_enc_err | 106895674262107225796969405803811235722793988206538762691432322030129412374160 | None | ||
| sram_ctrl_readback_err | 23950869764128994750776595288450393195498024137785215602049957912307656148645 | None | ||
| sram_ctrl_mubi_enc_err | 42186223347453198721874714276229002157428962681479606062352649694016767942921 | None | ||
| sram_ctrl_readback_err | 46199894328912549054461527201971549291983919813342030503173311420586852992267 | None | ||
| sram_ctrl_mubi_enc_err | 1947001308010592964939391001632227456549044402203674877284581080347934259839 | None | ||
| sram_ctrl_readback_err | 57060654423517028260566913461150221766362600456833509254018365915018984499806 | None | ||
| sram_ctrl_mubi_enc_err | 89083982107882196322646058239171093646075470140673429697620632673542808389334 | None | ||