Simulation Results: adc_ctrl

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.60 %
  • code
  • 98.53 %
  • assert
  • 96.92 %
  • func
  • 19.34 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 95.08 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
94.35%
V2S
86.67%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
adc_ctrl_smoke 19.800s 5671.273us 10 10 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 4.040s 1083.779us 1 1 100.00
csr_rw 5 5 100.00
adc_ctrl_csr_rw 2.380s 458.626us 5 5 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 8.900s 1536.589us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.430s 634.367us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.550s 415.398us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
adc_ctrl_csr_rw 2.380s 458.626us 5 5 100.00
adc_ctrl_csr_aliasing 1.430s 634.367us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 10 10 100.00
adc_ctrl_filters_polled 133.340s 55409.187us 10 10 100.00
filters_polled_fixed 10 10 100.00
adc_ctrl_filters_polled_fixed 136.830s 53237.000us 10 10 100.00
filters_interrupt 10 10 100.00
adc_ctrl_filters_interrupt 141.450s 52720.780us 10 10 100.00
filters_interrupt_fixed 10 10 100.00
adc_ctrl_filters_interrupt_fixed 151.320s 54506.373us 10 10 100.00
filters_wakeup 10 10 100.00
adc_ctrl_filters_wakeup 195.450s 70694.695us 10 10 100.00
filters_wakeup_fixed 10 10 100.00
adc_ctrl_filters_wakeup_fixed 161.160s 65946.494us 10 10 100.00
filters_both 10 10 100.00
adc_ctrl_filters_both 162.260s 61494.056us 10 10 100.00
clock_gating 2 10 20.00
adc_ctrl_clock_gating 52.970s 47150.453us 2 10 20.00
poweron_counter 10 10 100.00
adc_ctrl_poweron_counter 15.720s 4637.013us 10 10 100.00
lowpower_counter 10 10 100.00
adc_ctrl_lowpower_counter 106.430s 31663.375us 10 10 100.00
fsm_reset 10 10 100.00
adc_ctrl_fsm_reset 315.440s 119236.049us 10 10 100.00
stress_all 8 10 80.00
adc_ctrl_stress_all 440.630s 174728.962us 8 10 80.00
alert_test 10 10 100.00
adc_ctrl_alert_test 2.370s 478.383us 10 10 100.00
intr_test 10 10 100.00
adc_ctrl_intr_test 2.340s 513.079us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
adc_ctrl_tl_errors 4.010s 590.993us 25 25 100.00
tl_d_illegal_access 25 25 100.00
adc_ctrl_tl_errors 4.010s 590.993us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
adc_ctrl_csr_hw_reset 4.040s 1083.779us 1 1 100.00
adc_ctrl_csr_rw 2.380s 458.626us 5 5 100.00
adc_ctrl_csr_aliasing 1.430s 634.367us 1 1 100.00
adc_ctrl_same_csr_outstanding 9.090s 2433.541us 5 5 100.00
tl_d_partial_access 12 12 100.00
adc_ctrl_csr_hw_reset 4.040s 1083.779us 1 1 100.00
adc_ctrl_csr_rw 2.380s 458.626us 5 5 100.00
adc_ctrl_csr_aliasing 1.430s 634.367us 1 1 100.00
adc_ctrl_same_csr_outstanding 9.090s 2433.541us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 26 30 86.67
adc_ctrl_sec_cm 16.310s 7337.053us 5 5 100.00
adc_ctrl_tl_intg_err 25.830s 7856.861us 21 25 84.00
sec_cm_bus_integrity 21 25 84.00
adc_ctrl_tl_intg_err 25.830s 7856.861us 21 25 84.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
adc_ctrl_stress_all_with_rand_reset 16.760s 4152.363us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 12 test runs
adc_ctrl_clock_gating 7246741362538320821353066012227946303333237398535558970920323161081553995990 392
UVM_INFO @ 10776711631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 30288913631833331792655806901628514220757727438502066568760332084635849176229 392
UVM_INFO @ 7528023025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 98613654452840030958850357932589729361180994786839961260374755179811831583371 399
UVM_INFO @ 24962081857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 69690809508025090106172874866081128487676422397233588597989166827085515607345 400
UVM_INFO @ 23899888776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 22098430685590366601479381533072212409294091190983857095370840672322881989609 392
UVM_INFO @ 7082253419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 63416298015126652523077387616794853099146642463590873458815652165560271695341 430
UVM_INFO @ 6296798260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 58834938719710780979640491632455356669359333171610855732431576298432323393843 425
UVM_INFO @ 2781765375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 67419800106771654492765188946943166406551874683348103455280316323436814491786 392
UVM_INFO @ 16635484185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 50583473239708014233635835459094739597347581894561117248235704494999052364972 405
UVM_INFO @ 6273704384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 81782163006883254076468879312932348206285107968232388998835799947155737149496 416
UVM_INFO @ 35615657741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 36067643650441979184239941078456199631694593162173572847768184926561483963808 392
UVM_INFO @ 1468020746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 27877647649822266096314080015971245636750554976779444128494289198628300889138 392
UVM_INFO @ 1209209573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [adc_ctrl_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 4 test runs
adc_ctrl_tl_intg_err 60401345758850324447313146388470857159310385724305089729966697852723087326394 448
UVM_INFO @ 2946596400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_tl_intg_err 1438480447938041518389504446519271064020377148692017217459094151960387546586 445
UVM_INFO @ 2140177644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_tl_intg_err 43895972647197152991894738261995976952224249286748743995330155334409697180482 460
UVM_INFO @ 3790499376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_tl_intg_err 29630573042610176194869382507399948231351222495476698103099532679639216889244 532
UVM_INFO @ 6265946781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---