Simulation Results: aes/masked

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.42 %
  • code
  • 96.55 %
  • assert
  • 98.38 %
  • func
  • 97.32 %
  • block
  • 96.88 %
  • line
  • 97.79 %
  • branch
  • 92.65 %
  • toggle
  • 97.99 %
  • FSM
  • 97.78 %
Validation stages
V1
95.83%
V2
97.71%
V2S
91.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 154.949us 1 1 100.00
smoke 10 10 100.00
aes_smoke 7.000s 260.686us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 127.473us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 2.000s 83.808us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 14.000s 4015.878us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 223.139us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
aes_csr_mem_rw_with_rand_reset 18.000s 10012.616us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 2.000s 83.808us 5 5 100.00
aes_csr_aliasing 3.000s 223.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 70 70 100.00
aes_smoke 7.000s 260.686us 10 10 100.00
aes_config_error 9.000s 103.488us 50 50 100.00
aes_stress 6.000s 138.716us 10 10 100.00
key_length 70 70 100.00
aes_smoke 7.000s 260.686us 10 10 100.00
aes_config_error 9.000s 103.488us 50 50 100.00
aes_stress 6.000s 138.716us 10 10 100.00
back2back 35 35 100.00
aes_stress 6.000s 138.716us 10 10 100.00
aes_b2b 77.000s 941.415us 25 25 100.00
backpressure 10 10 100.00
aes_stress 6.000s 138.716us 10 10 100.00
multi_message 95 95 100.00
aes_smoke 7.000s 260.686us 10 10 100.00
aes_config_error 9.000s 103.488us 50 50 100.00
aes_stress 6.000s 138.716us 10 10 100.00
aes_alert_reset 203.000s 8304.023us 25 25 100.00
failure_test 85 85 100.00
aes_man_cfg_err 3.000s 63.578us 10 10 100.00
aes_config_error 9.000s 103.488us 50 50 100.00
aes_alert_reset 203.000s 8304.023us 25 25 100.00
trigger_clear_test 10 10 100.00
aes_clear 36.000s 1661.259us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 14.000s 430.114us 1 1 100.00
reset_recovery 25 25 100.00
aes_alert_reset 203.000s 8304.023us 25 25 100.00
stress 10 10 100.00
aes_stress 6.000s 138.716us 10 10 100.00
sideload 20 20 100.00
aes_stress 6.000s 138.716us 10 10 100.00
aes_sideload 7.000s 376.487us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 8.000s 796.279us 10 10 100.00
stress_all 5 10 50.00
aes_stress_all 10800.000s 0.000us 5 10 50.00
alert_test 10 10 100.00
aes_alert_test 3.000s 54.522us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 5.000s 329.892us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 5.000s 329.892us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aes_csr_hw_reset 2.000s 127.473us 1 1 100.00
aes_csr_rw 2.000s 83.808us 5 5 100.00
aes_csr_aliasing 3.000s 223.139us 1 1 100.00
aes_same_csr_outstanding 3.000s 93.633us 5 5 100.00
tl_d_partial_access 12 12 100.00
aes_csr_hw_reset 2.000s 127.473us 1 1 100.00
aes_csr_rw 2.000s 83.808us 5 5 100.00
aes_csr_aliasing 3.000s 223.139us 1 1 100.00
aes_same_csr_outstanding 3.000s 93.633us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 5 10 50.00
aes_reseed 46.000s 2773.692us 5 10 50.00
fault_inject 594 660 90.00
aes_fi 14.000s 404.919us 1 10 10.00
aes_control_fi 61.000s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 325 350 92.86
shadow_reg_update_error 18 20 90.00
aes_shadow_reg_errors 24.000s 10008.216us 18 20 90.00
shadow_reg_read_clear_staged_value 18 20 90.00
aes_shadow_reg_errors 24.000s 10008.216us 18 20 90.00
shadow_reg_storage_error 18 20 90.00
aes_shadow_reg_errors 24.000s 10008.216us 18 20 90.00
shadowed_reset_glitch 18 20 90.00
aes_shadow_reg_errors 24.000s 10008.216us 18 20 90.00
shadow_reg_update_error_with_csr_rw 18 20 90.00
aes_shadow_reg_errors_with_csr_rw 4.000s 292.955us 18 20 90.00
tl_intg_err 29 30 96.67
aes_sec_cm 10.000s 966.688us 5 5 100.00
aes_tl_intg_err 5.000s 1698.264us 24 25 96.00
sec_cm_bus_integrity 24 25 96.00
aes_tl_intg_err 5.000s 1698.264us 24 25 96.00
sec_cm_lc_escalate_en_intersig_mubi 25 25 100.00
aes_alert_reset 203.000s 8304.023us 25 25 100.00
sec_cm_main_config_shadow 18 20 90.00
aes_shadow_reg_errors 24.000s 10008.216us 18 20 90.00
sec_cm_gcm_config_shadow 18 20 90.00
aes_shadow_reg_errors 24.000s 10008.216us 18 20 90.00
sec_cm_main_config_sparse 136 145 93.79
aes_smoke 7.000s 260.686us 10 10 100.00
aes_stress 6.000s 138.716us 10 10 100.00
aes_alert_reset 203.000s 8304.023us 25 25 100.00
aes_core_fi 82.000s 10013.123us 91 100 91.00
sec_cm_gcm_config_sparse 151 160 94.38
aes_config_error 9.000s 103.488us 50 50 100.00
aes_stress 6.000s 138.716us 10 10 100.00
aes_core_fi 82.000s 10013.123us 91 100 91.00
sec_cm_aux_config_shadow 18 20 90.00
aes_shadow_reg_errors 24.000s 10008.216us 18 20 90.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 4.000s 105.117us 10 10 100.00
aes_stress 6.000s 138.716us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 6.000s 138.716us 10 10 100.00
aes_sideload 7.000s 376.487us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 4.000s 105.117us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 4.000s 105.117us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 4.000s 105.117us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 4.000s 105.117us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 4.000s 105.117us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 6.000s 138.716us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 6.000s 138.716us 10 10 100.00
sec_cm_main_fsm_sparse 1 10 10.00
aes_fi 14.000s 404.919us 1 10 10.00
sec_cm_main_fsm_redun 619 685 90.36
aes_fi 14.000s 404.919us 1 10 10.00
aes_control_fi 61.000s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 325 350 92.86
aes_ctr_fi 4.000s 160.008us 25 25 100.00
sec_cm_cipher_fsm_sparse 1 10 10.00
aes_fi 14.000s 404.919us 1 10 10.00
sec_cm_cipher_fsm_redun 594 660 90.00
aes_fi 14.000s 404.919us 1 10 10.00
aes_control_fi 61.000s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 325 350 92.86
sec_cm_cipher_ctr_redun 325 350 92.86
aes_cipher_fi 61.000s 0.000us 325 350 92.86
sec_cm_ctr_fsm_sparse 1 10 10.00
aes_fi 14.000s 404.919us 1 10 10.00
sec_cm_ctr_fsm_redun 294 335 87.76
aes_fi 14.000s 404.919us 1 10 10.00
aes_control_fi 61.000s 0.000us 268 300 89.33
aes_ctr_fi 4.000s 160.008us 25 25 100.00
sec_cm_ghash_fsm_sparse 1 10 10.00
aes_fi 14.000s 404.919us 1 10 10.00
sec_cm_ctrl_sparse 619 685 90.36
aes_fi 14.000s 404.919us 1 10 10.00
aes_control_fi 61.000s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 325 350 92.86
aes_ctr_fi 4.000s 160.008us 25 25 100.00
sec_cm_main_fsm_global_esc 25 25 100.00
aes_alert_reset 203.000s 8304.023us 25 25 100.00
sec_cm_main_fsm_local_esc 619 685 90.36
aes_fi 14.000s 404.919us 1 10 10.00
aes_control_fi 61.000s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 325 350 92.86
aes_ctr_fi 4.000s 160.008us 25 25 100.00
sec_cm_cipher_fsm_local_esc 619 685 90.36
aes_fi 14.000s 404.919us 1 10 10.00
aes_control_fi 61.000s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 325 350 92.86
aes_ctr_fi 4.000s 160.008us 25 25 100.00
sec_cm_ctr_fsm_local_esc 294 335 87.76
aes_fi 14.000s 404.919us 1 10 10.00
aes_control_fi 61.000s 0.000us 268 300 89.33
aes_ctr_fi 4.000s 160.008us 25 25 100.00
sec_cm_ghash_fsm_local_esc 1 10 10.00
aes_fi 14.000s 404.919us 1 10 10.00
sec_cm_data_reg_local_esc 594 660 90.00
aes_fi 14.000s 404.919us 1 10 10.00
aes_control_fi 61.000s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 325 350 92.86
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 62.000s 20256.955us 0 10 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 26 test runs
aes_control_fi 112006752052689378524017403169578278682948925163676563287720208583558506829701 None
aes_stress_all 96892671065729989794662832334772210436024794552000202618679571591330909355509 None
aes_control_fi 56568833151304319818378872823913799556205864733863268824244607602397586611060 None
aes_control_fi 106309923199818032781714089574173593930160463315505243857544030889161970079139 None
aes_control_fi 95338680595146378824507861508755012322787247777482468335939132064462864548766 None
aes_cipher_fi 70615741759958787063761577442972732242776546934660986511364504209345024450693 None
aes_control_fi 38764921927070234278639028914956285101660407122468710428361776590551421336257 None
aes_cipher_fi 28391318122838633181909602175922899331643350026154290799956327954821509942928 None
aes_control_fi 57767275225567266065875406590775370223343034306644065772339306181581116141430 None
aes_control_fi 98761090315705929130688462518586002296323267906544999459564845777515295442046 None
aes_cipher_fi 30667331664793736016013042230856303827770849503852271448776740055165153088897 None
aes_control_fi 47935818512215718195227865724663713694586285637524976494410889402845128194968 None
aes_control_fi 16297424892282079781727527067983126217542789187102196390258797252820639979401 None
aes_control_fi 86889003738937312295997933382005220863650287111496112033171067411264118620068 None
aes_control_fi 80028325689109508535617323464067593403756355111492693589055580965648385734453 None
aes_control_fi 73490881945668169726920807870642092309884043045175809489181983068975280144590 None
aes_control_fi 35275647418342980742594700967590015160212933973458531675264021036461198605500 None
aes_control_fi 20918126777878504179259048252983902245530300204258895120087621335991467574677 None
aes_control_fi 10223958214025491209542782018701452961936393391315980535213406552984960575967 None
aes_cipher_fi 32004733374284965278792931222641424727429093443126886820103323549235762870138 None
aes_control_fi 98063083484284738502432125209559806343214187343795512112643144366259498237668 None
aes_control_fi 10221377570756493881101488149100415809686157589023390549419569845441452568417 None
aes_cipher_fi 77847627518052168268762950428849971202714804367037795553778556520954637747358 None
aes_cipher_fi 45534459078710573193243614539834358860458481328929028488981154746315345361698 None
aes_cipher_fi 67128272315030516595115032200746498813726178986041153207181832330783815933253 None
aes_cipher_fi 5456294865357624054535728825806670371340957123764714316727647481021114676351 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 17 test runs
aes_cipher_fi 80581019156465144862930634636054759188706695498932912493201049600850037111913 142
UVM_INFO @ 10058526243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 79681974281787474960588165624425705041032224320834113151232290054083721277051 143
UVM_INFO @ 10009194009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 155810647439256448433986958720448190065417797542940131553401105413853667006 143
UVM_INFO @ 10047509443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 103819972280568794775421615080102326394515706196163931463095684196836598294918 146
UVM_INFO @ 10022893339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 62156880206544540567654423403343729007821760423551827618951492460847978396160 149
UVM_INFO @ 10020871212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 82208793512186132657107892606618783184720423974156751146961110024326525210562 151
UVM_INFO @ 10086586333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 39852617218421553354568988318877362226969790071374813996236013044211606185404 151
UVM_INFO @ 10007346269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 38797224024810170090611099669793712625462818868643346038868084092603145040038 150
UVM_INFO @ 10018417463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 68071661804945126712496730672809393440650071552871633380541754881949588432969 141
UVM_INFO @ 10055627260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 25144598708260650315847454133531285026127463841302777959357700614615602064498 154
UVM_INFO @ 10018382289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 89278968692264310705716213857708500482612704509699962803754975983572579185988 143
UVM_INFO @ 10006446165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 41136403843156969129459959519024817750467038829080352372330077610515219217280 145
UVM_INFO @ 10039277291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 6797030487912796695690046898015902611874713168561542325670450266116056896357 150
UVM_INFO @ 10021867658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 82896623183733557770498090516665744743263188725277281109958135475580471653581 149
UVM_INFO @ 10030441992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 12002544556482527264137093809758135556802866289021447473557294386276360839278 143
UVM_INFO @ 10304117761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 86246975006331333512420560445011221887763744666126742004693225740465238438401 140
UVM_INFO @ 10004335792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 33434540133416452052601804897255138869344121700484378035924918441788832494776 144
UVM_INFO @ 10068303354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 15 test runs
aes_control_fi 27879354878270322742801570199849810789065285956894098406818299083102381069176 142
UVM_INFO @ 10006684539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 10690499553011880537950779324145134192121201840413572821768230102359908491647 142
UVM_INFO @ 10006613038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 35260215642730115452254790802276760318507704920931796783903198559570956283885 145
UVM_INFO @ 10111772909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 74155369494263237846905028911547442438198458476240312106575303797306458981521 151
UVM_INFO @ 10025012603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 66730694891959958145108636182063206183563726431675007481902600168453283982599 144
UVM_INFO @ 10092452493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 94709969155450210826830015229036583972296336967626098203762837958363834874361 143
UVM_INFO @ 10014992417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 34791875516395148472085704136907266087816857589947268061206480137619814523573 145
UVM_INFO @ 10024515726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 85042790157592053216835288134217528496172220558148572650219232462377997432980 140
UVM_INFO @ 10019266612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 40700441589262935453065186927606012894638687518847965409564407745508798599929 137
UVM_INFO @ 10017874974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 41386304553368545108050777204423584038821512288818960157004702174740189355228 144
UVM_INFO @ 10013621029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 84812125341290364008921865051702368360730124259412090571579590894509375275495 141
UVM_INFO @ 10010383886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 111898121909333577194728068643732523992438066162708667488734113595937878061886 141
UVM_INFO @ 10148066397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 11086698085763066425502152426101875796697941119430597764027334232983409107556 148
UVM_INFO @ 10006742724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 94551777991990988600822445683177243285678816763298174765119390016071526318152 144
UVM_INFO @ 10007115790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 80597619913981892505875792680323888376310065771669302159577177906596661342617 143
UVM_INFO @ 10016559488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 12 test runs
aes_reseed 85986541523302800946552735580929350575188019909301528480313227707012654708737 12198
UVM_INFO @ 268802010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 38693942148631531382307145329092262048915563511884144326660900343756694839148 68212
UVM_INFO @ 1953092604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 82322477916807045321208115932309438221191780520226778814764625544251972593271 226
UVM_INFO @ 810262911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 27365667005847378858810409739580998056383391203631137770644906459347203318020 11994
UVM_INFO @ 219028151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 9925450247142086573876896707453738399734690528556165951906245373036114854713 10770
UVM_INFO @ 156945978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 80976584304961664956811608462660184710194548531190536129274977896310951216895 26910
UVM_INFO @ 101239932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 15601322596336606045459781507333309327464475387433413149730720280062619887377 1937
UVM_INFO @ 35295732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 52810909933911685364580326965311703593405863111348055353950945150343074061777 34382
UVM_INFO @ 1225314397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 74607521878335161922580901336306635104405285202864836268533572068942470572010 336
UVM_INFO @ 638505713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 50536439160481461716718932770328993342936343296412351621088174540576006958603 102613
UVM_INFO @ 1583313743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 71710669339147735518472096837651401836395652969594027053914290692923675203062 202
UVM_INFO @ 98683043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 83679288514881336818818606429896372678807479163900445811458810514402915522018 3208
UVM_INFO @ 58243118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 9 test runs
aes_fi 7303764225203814334088499549751444850122817986445871487209522773647671136477 8123
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
aes_fi 62516812991212530676714840854355564746369387105153573542114445288476622610941 18751
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
aes_fi 63089358214206882597235979703547927575401547294541432722469621952330456468745 8961
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
aes_fi 85858334343610161072300621416483816200989796266420686870185775964700825268842 31731
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
aes_fi 93488767220326746734828390427206984264334351752627994955174196347805671152944 14963
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
aes_fi 23883221463887238682276029893441466325338681284847776254593297485436821460713 17749
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
aes_fi 8767818624439569399132632706302391332385706582837326596655794735792606716389 12758
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
aes_fi 93247989294098014303303136195853918888860319458308470792076056114479471529045 10545
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
aes_fi 73564751518874175526852183495879704898348178517137340634641162677166611426038 17148
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 9 test runs
aes_core_fi 35978117914041830286280869206146902639275680777677673814715472069901324463954 139
UVM_INFO @ 10018563463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 88291830172236489883004264221714674994284818729018814971544033352361740082729 143
UVM_INFO @ 10010450752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 8054448528007877118329360863526027430192337285762348525440483053687995187491 142
UVM_INFO @ 10006944166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 50951503914806746698133847584330088633931885063097906057509779498907151661919 152
UVM_INFO @ 10013122854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 42661887207046566579233636946368327303883981448486455121038214818422899870991 142
UVM_INFO @ 10002497286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 44155083114429923843111605356471252928507665863905795529115655169052815042918 147
UVM_INFO @ 10011675112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 21546162331724566808209687251551538230699162147011871583760146734505575447005 147
UVM_INFO @ 10013054936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 55592598959300199005768833423042834923127311929132483873172478453305409761558 144
UVM_INFO @ 10013600550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 114091064132086819845650885579799206465937057584873742470317762069844385518265 144
UVM_INFO @ 10014464280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 5 test runs
aes_stress_all_with_rand_reset 98378866942923302381478091749090132705969887749874569988530097409560164044399 696
UVM_INFO @ 1583703076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 46043473228079589631256331051580593529406228394370264682377792180398036536055 1007
UVM_INFO @ 20256955429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 57863728378833130082834961302688166330213652912644338409363369003268299385229 240
UVM_INFO @ 340376517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 90408768945797770299732856212399368242457109902154602225563273255836478116665 317
UVM_INFO @ 417119005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 68704246492983863949947549246887431287210347602188496877665508098206485656385 269
UVM_INFO @ 1882225723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1391) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 2 test runs
aes_shadow_reg_errors_with_csr_rw 68007964926705539933860876506794360498492648561654701500902698744590297083906 106
UVM_INFO @ 89749113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_shadow_reg_errors_with_csr_rw 53760353121580819177983990539537105036484145692462537083300507405104828138510 107
UVM_INFO @ 292954661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 44536598662256351079588110618751808429784634007002878573397714154663451086116 109
UVM_INFO @ 4214923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [aes_common_vseq] wait timeout occurred! 1 test run
aes_csr_mem_rw_with_rand_reset 98770069183689752414929397959984674286654059140463367195570086752803393372902 117
UVM_INFO @ 10012615680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:97) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 80678753020037079220532526742359077627233965913711764010766869928506287909610 109
UVM_INFO @ 34055513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors 46118606306189262461209910999430430966284232558587854760928838703478013510506 106
UVM_INFO @ 37946757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:336) [aes_common_vseq] ctrl_shadowed update_err alert timeout 1 test run
aes_shadow_reg_errors 96014127117258229193442298732858746518661833029728437924773718534872316411100 106
UVM_INFO @ 10008215978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [aes_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
aes_tl_intg_err 19974052094815267046947963611877479165881882696510976593964418542944717027548 190
UVM_INFO @ 410766813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---