| V1 |
|
100.00% |
| V2 |
|
86.39% |
| V2S |
|
94.63% |
| V3 |
|
30.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 70.940s | 3978.202us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.380s | 22.121us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 7.130s | 40.056us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 317.380s | 20683.129us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 37.190s | 1826.554us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 12.680s | 591.700us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 7.130s | 40.056us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 37.190s | 1826.554us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 340.370s | 5321.872us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 94.310s | 1484.086us | 50 | 50 | 100.00 | |
| entropy | 23 | 25 | 92.00 | |||
| alert_handler_entropy | 3600.146s | 0.000us | 23 | 25 | 92.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 87.130s | 4518.541us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 70.940s | 3978.202us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 84.660s | 1381.251us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 97.960s | 17484.833us | 50 | 50 | 100.00 | |
| ping_timeout | 21 | 50 | 42.00 | |||
| alert_handler_ping_timeout | 644.820s | 30566.698us | 21 | 50 | 42.00 | |
| lpg | 82 | 100 | 82.00 | |||
| alert_handler_lpg | 3600.210s | 0.000us | 41 | 50 | 82.00 | |
| alert_handler_lpg_stub_clk | 3600.410s | 0.000us | 41 | 50 | 82.00 | |
| stress_all | 50 | 50 | 100.00 | |||
| alert_handler_stress_all | 5689.940s | 297753.850us | 50 | 50 | 100.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 26.550s | 1230.182us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 5.720s | 58.229us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 3.120s | 44.319us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 33.360s | 1372.757us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 33.360s | 1372.757us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.380s | 22.121us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 7.130s | 40.056us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 37.190s | 1826.554us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 58.510s | 4694.574us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.380s | 22.121us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 7.130s | 40.056us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 37.190s | 1826.554us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 58.510s | 4694.574us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 387.010s | 5571.105us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 387.010s | 5571.105us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 387.010s | 5571.105us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 387.010s | 5571.105us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1448.990s | 17159.158us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 37.200s | 546.792us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 100.490s | 8696.707us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 100.490s | 8696.707us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 387.010s | 5571.105us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 70.940s | 3978.202us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 70.940s | 3978.202us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 70.940s | 3978.202us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 70.940s | 3978.202us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 87.130s | 4518.541us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 41 | 50 | 82.00 | |||
| alert_handler_lpg | 3600.210s | 0.000us | 41 | 50 | 82.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 87.130s | 4518.541us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 23 | 25 | 92.00 | |||
| alert_handler_entropy | 3600.146s | 0.000us | 23 | 25 | 92.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 23 | 25 | 92.00 | |||
| alert_handler_entropy | 3600.146s | 0.000us | 23 | 25 | 92.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 37.200s | 546.792us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 37.200s | 546.792us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 37.200s | 546.792us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 37.200s | 546.792us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 37.200s | 546.792us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 37.200s | 546.792us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 37.200s | 546.792us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 37.200s | 546.792us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 37.200s | 546.792us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 3 | 10 | 30.00 | |||
| alert_handler_stress_all_with_rand_reset | 352.650s | 6827.278us | 3 | 10 | 30.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 22 test runs | |||
| alert_handler_ping_timeout | 48752163802835414245967698159653943363576694751764903400994663089393217431502 | 114 |
UVM_INFO @ 5298440004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 59043063603758704522565639849185388459198389421079332987213145183078665707936 | 114 |
UVM_INFO @ 22875301063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 82614012580231437617996934029693505716765093252943704274634678759557053259191 | 96 |
UVM_INFO @ 10581554913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 58704247928644807543749584138754179450121707522798381764552773766566787798505 | 120 |
UVM_INFO @ 24378236270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 53034968944167842610724514447365891070647227059517868852219238154164687608428 | 93 |
UVM_INFO @ 5286979450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 51850555077071658732165056435359428146155577787069760990925873723161793896508 | 111 |
UVM_INFO @ 2726787536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 45323457517014510726356166763785821390378866241704826671932537813536783298915 | 123 |
UVM_INFO @ 20859159241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 94198408311174110243264437994105565603304552034338562678904239380953931529051 | 99 |
UVM_INFO @ 7539892674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 51750855189128120093731210591429034466487322402468581882844763413823821853282 | 93 |
UVM_INFO @ 3567696175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 79594642576002983944710009409788128720712777192222074895314250760083592280356 | 99 |
UVM_INFO @ 1204460725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 7421627436825381920398995886346565771761985597236429424699006439422879098155 | 117 |
UVM_INFO @ 96591919420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 35012292798637184209380586965183910028856328282141543358111932107545443007727 | 120 |
UVM_INFO @ 17786698998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 8024269996948808910428245259714249226832324301648211085648350236391209610893 | 129 |
UVM_INFO @ 141451461943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 37745089737319475929188380571167411152015317039843410173877024104313055430943 | 108 |
UVM_INFO @ 10554569471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 40973864561773756541160931404911846491263263502049191680408093801468414479394 | 120 |
UVM_INFO @ 16994465685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 83164885437503176973832088784324716251495672907722835323222538864270298649031 | 95 |
UVM_INFO @ 8030475804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 53372149197831557040252948326280944657937083947273885365112201346951304090305 | 108 |
UVM_INFO @ 3647795824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 20064355008015371275016771912174192809143556833976540560346244085142384123456 | 120 |
UVM_INFO @ 20370582717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 110237896964871406361528090236531876347247890629009770172911262186567576147241 | 141 |
UVM_INFO @ 10227554464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 74708246259476192529105417077088145183304819692523188831147511816177783025160 | 105 |
UVM_INFO @ 3164091050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 16429863514811935714932178789149234007618510397037048347592426614483127099364 | 87 |
UVM_INFO @ 173017650191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 26873661395508106575402632823519340535860547746053309691326502664275177091565 | 90 |
UVM_INFO @ 7264332616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 36047041720423563434626718042954991804110091831341581680340565538644091333195 | 202 |
UVM_INFO @ 368288991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 64776979189822098125228764526351591570205046078970877416677708195510975014755 | 176 |
UVM_INFO @ 103144822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 32595507060902687702224207817971108832534341626485624201620787208634114019286 | 188 |
UVM_INFO @ 792357628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 29178623570957899123267943308807736527611954431191602681386815045837666309321 | 154 |
UVM_INFO @ 204617803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 68090730709355084127811098099866993973057268333820244195312887479063591767070 | 178 |
UVM_INFO @ 416510150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 6275144859147101727633998379448164776853867711039926532775277652856587935171 | 168 |
UVM_INFO @ 91632778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 101616872135910652774029455454359182017850036098088655666806716440729227543813 | 178 |
UVM_INFO @ 511934875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 102114104795379654096899535327362512145398373502450445499208365464020763102822 | 202 |
UVM_INFO @ 299283633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 93527792844776081490842180686475958561050478927424640123373226184820824792326 | 204 |
UVM_INFO @ 458956240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 62827223928893133024375608843572961138943066464513086848963581242248264070317 | 208 |
UVM_INFO @ 990994066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 41025287847668759545511634877932580683594838737356280936928812362467539641355 | 176 |
UVM_INFO @ 98584408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 73203303468373051270091452832642653201126098869980825371245935796528664418341 | 184 |
UVM_INFO @ 874724812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 5118688589451672965094468295637531920530006583112457938430581572312109803884 | 206 |
UVM_INFO @ 291276985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 43838114153141050641393810387555231687541439036141348885499204550402929377001 | 154 |
UVM_INFO @ 141944266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 18586139993222527170033816348644600201705120635366323928290348393186325600488 | 212 |
UVM_INFO @ 1230181539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 5279356737845509134552171439468207246975167045256968417380913942619055320491 | 158 |
UVM_INFO @ 2203492212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 41445354312375692465901417534011457634748512566929337635977891908416134376919 | 172 |
UVM_INFO @ 347173439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 33549182865379739388389033991700022072683602717216147650794262990865035934260 | 210 |
UVM_INFO @ 78227249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 1653522698424131632454271909736348265703608987499073208834994823713174873422 | 188 |
UVM_INFO @ 152726920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 106053738755298506067099565868440585235138450752676575098740054855672201067985 | 202 |
UVM_INFO @ 1408901821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 17 test runs | |||
| alert_handler_lpg | 79934954099350334010862285346390075274009796872547116539852714868548120760677 | None | ||
| alert_handler_lpg_stub_clk | 21186280512860975746532044817057313372079754499783098553638381976789160376635 | None | ||
| alert_handler_lpg | 34494525074986465613136895384137083288517338876242900196348745042491930522380 | None | ||
| alert_handler_lpg | 25497214872135166517579344522520501225301627077443776865528868953954583864908 | None | ||
| alert_handler_lpg_stub_clk | 28396064121881252021913117781295495151853578886929366850688933249644840848594 | None | ||
| alert_handler_entropy | 4407450854588267827311440706272535685608987071206591638307438103354106546512 | None | ||
| alert_handler_lpg_stub_clk | 91042085144220588228539912636056626579135782437336625595200099684704391726588 | None | ||
| alert_handler_entropy | 65556218513373151892404663298792546931171451019114578702154997274404076977278 | None | ||
| alert_handler_lpg_stub_clk | 34126823600512995975740880606676204170703703463255615628883429028699124479783 | None | ||
| alert_handler_lpg_stub_clk | 62548559471102090949135852970104459770948161281685484464245856722582747196233 | None | ||
| alert_handler_lpg | 20606210507559791677554009043246849033779034630036474614677320264496595067456 | None | ||
| alert_handler_lpg | 16808697558431347594888086914006472674469833761838517378909817950359116841148 | None | ||
| alert_handler_lpg_stub_clk | 108472947653169379615210533412404388174121979304707212046367050026109290801238 | None | ||
| alert_handler_lpg | 108707833372591111707039872017491074810871174588886668621650360192826820424543 | None | ||
| alert_handler_lpg_stub_clk | 113026973168078266015232559641250332708412806194929959315195162986930388394080 | None | ||
| alert_handler_lpg | 93418614938653926718806354577161452777454960139133778562900943823422516480751 | None | ||
| alert_handler_lpg_stub_clk | 31550502332834901269592832990411503814304600115903523902646442989834892349511 | None | ||
| UVM_ERROR (alert_handler_scoreboard.sv:604) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 8 test runs | |||
| alert_handler_ping_timeout | 109847851919390518666227710920189741304824945363352296551849254655345802083711 | 86 |
UVM_INFO @ 113018815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 97230566447064937501556440418624977539357562047047984187075436785004315636711 | 86 |
UVM_INFO @ 1486633444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 101945984226508558857990002216236702508133823872930731654165283136864362484573 | 86 |
UVM_INFO @ 644777883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 105667571622384092156827795731031669905894078809638538336460079945816959092266 | 86 |
UVM_INFO @ 298180316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 104972919747498050652859901927018622445239710991711972107824908561303965066252 | 86 |
UVM_INFO @ 456149283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 102689505595583252573732170845524408630925951445282154925377256745263131498725 | 86 |
UVM_INFO @ 1252056131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 46231212083590071544614605231561794218923465373469255014652300408958026134392 | 86 |
UVM_INFO @ 10884831664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 6873914361729771276010551308122191945715886262321047560603290865987299479645 | 86 |
UVM_INFO @ 325944833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 7 test runs | |||
| alert_handler_stress_all_with_rand_reset | 74429348325668482815806252908119991156195290789430948856400695409421715422354 | 191 |
UVM_INFO @ 3622106356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 76426168105209002905329283988877403340170820585014772401566436696079602470412 | 101 |
UVM_INFO @ 1804289641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 72191942444070636016384949994861498805169032389949946494492417288902757430380 | 98 |
UVM_INFO @ 2186745411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 103010546308358486000160839443491703551964153664785577695373205751049958245403 | 89 |
UVM_INFO @ 2734460257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 64987201658902476925200240916812126753833692436187645442947617998088487438959 | 139 |
UVM_INFO @ 5685416301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 43120904243623418691622018463303527887459662969054896686074553885968769950615 | 135 |
UVM_INFO @ 3382795839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 79412553945378752249506969808651579252197381353261272161396035187226032407156 | 89 |
UVM_INFO @ 211323786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertPingFail) | 2 test runs | |||
| alert_handler_lpg | 60032272457379906149671472739608456675482031589121929143490200803555654225148 | 88 |
UVM_INFO @ 70971467328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg_stub_clk | 38918281481569450531204123140865551909898914140295586335762376562633882347496 | 87 |
UVM_INFO @ 62934995669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|