Simulation Results: aon_timer

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.09 %
  • code
  • 99.17 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • line
  • 99.09 %
  • branch
  • 98.56 %
  • cond
  • 99.05 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
aon_timer_smoke 2.220s 723.271us 5 5 100.00
csr_hw_reset 1 1 100.00
aon_timer_csr_hw_reset 3.260s 1076.688us 1 1 100.00
csr_rw 5 5 100.00
aon_timer_csr_rw 1.610s 424.804us 5 5 100.00
csr_bit_bash 1 1 100.00
aon_timer_csr_bit_bash 3.150s 737.826us 1 1 100.00
csr_aliasing 1 1 100.00
aon_timer_csr_aliasing 1.330s 550.950us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aon_timer_csr_mem_rw_with_rand_reset 1.450s 525.514us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aon_timer_csr_rw 1.610s 424.804us 5 5 100.00
aon_timer_csr_aliasing 1.330s 550.950us 1 1 100.00
mem_walk 1 1 100.00
aon_timer_mem_walk 1.180s 336.066us 1 1 100.00
mem_partial_access 1 1 100.00
aon_timer_mem_partial_access 1.240s 314.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
prescaler 15 15 100.00
aon_timer_prescaler 40.070s 41416.077us 15 15 100.00
jump 5 5 100.00
aon_timer_jump 2.530s 745.664us 5 5 100.00
stress_all 15 15 100.00
aon_timer_stress_all 174.530s 86400.964us 15 15 100.00
alert_test 10 10 100.00
aon_timer_alert_test 1.520s 349.829us 10 10 100.00
intr_test 10 10 100.00
aon_timer_intr_test 1.860s 478.347us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aon_timer_tl_errors 3.200s 503.904us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aon_timer_tl_errors 3.200s 503.904us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aon_timer_csr_hw_reset 3.260s 1076.688us 1 1 100.00
aon_timer_csr_rw 1.610s 424.804us 5 5 100.00
aon_timer_csr_aliasing 1.330s 550.950us 1 1 100.00
aon_timer_same_csr_outstanding 6.710s 2217.551us 5 5 100.00
tl_d_partial_access 12 12 100.00
aon_timer_csr_hw_reset 3.260s 1076.688us 1 1 100.00
aon_timer_csr_rw 1.610s 424.804us 5 5 100.00
aon_timer_csr_aliasing 1.330s 550.950us 1 1 100.00
aon_timer_same_csr_outstanding 6.710s 2217.551us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 28 30 93.33
aon_timer_sec_cm 18.850s 7913.691us 5 5 100.00
aon_timer_tl_intg_err 20.570s 8248.365us 23 25 92.00
sec_cm_bus_integrity 23 25 92.00
aon_timer_tl_intg_err 20.570s 8248.365us 23 25 92.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_threshold 5 5 100.00
aon_timer_smoke_max_thold 2.480s 715.579us 5 5 100.00
min_threshold 5 5 100.00
aon_timer_smoke_min_thold 2.120s 633.217us 5 5 100.00
wkup_count_hi_cdc 5 5 100.00
aon_timer_wkup_count_cdc_hi 13.500s 3858.403us 5 5 100.00
custom_intr 10 10 100.00
aon_timer_custom_intr 2.150s 702.066us 10 10 100.00
alternating_on_off 5 5 100.00
aon_timer_alternating_enable_on_off 11.200s 4383.620us 5 5 100.00
stress_all_with_rand_reset 15 15 100.00
aon_timer_stress_all_with_rand_reset 48.600s 17326.544us 15 15 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [aon_timer_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 2 test runs
aon_timer_tl_intg_err 78443103555300422921892768020584572110433991982504315464676949440983971572636 157
UVM_INFO @ 3721356365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aon_timer_tl_intg_err 63307911780173313410054517836514456283161480301592577166457319268308375224637 96
UVM_INFO @ 766921196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---