Simulation Results: clkmgr

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.39 %
  • code
  • 98.87 %
  • assert
  • 96.47 %
  • func
  • 87.82 %
  • line
  • 99.29 %
  • branch
  • 99.06 %
  • cond
  • 95.98 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.62%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.470s 122.231us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.020s 26.618us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.350s 77.578us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 8.870s 1220.058us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.020s 38.700us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.160s 42.058us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.350s 77.578us 5 5 100.00
clkmgr_csr_aliasing 1.020s 38.700us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.170s 33.281us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.780s 154.315us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.570s 59.583us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.250s 105.916us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.470s 122.231us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 15.920s 2483.197us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 18.520s 2183.803us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 15.920s 2483.197us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 65.900s 14452.908us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.880s 114.759us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 7.860s 1362.854us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 7.860s 1362.854us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.020s 26.618us 1 1 100.00
clkmgr_csr_rw 1.350s 77.578us 5 5 100.00
clkmgr_csr_aliasing 1.020s 38.700us 1 1 100.00
clkmgr_same_csr_outstanding 2.330s 197.355us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.020s 26.618us 1 1 100.00
clkmgr_csr_rw 1.350s 77.578us 5 5 100.00
clkmgr_csr_aliasing 1.020s 38.700us 1 1 100.00
clkmgr_same_csr_outstanding 2.330s 197.355us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
clkmgr_sec_cm 8.660s 2190.323us 5 5 100.00
clkmgr_tl_intg_err 4.650s 958.841us 25 25 100.00
shadow_reg_update_error 20 20 100.00
clkmgr_shadow_reg_errors 3.880s 477.366us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
clkmgr_shadow_reg_errors 3.880s 477.366us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
clkmgr_shadow_reg_errors 3.880s 477.366us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
clkmgr_shadow_reg_errors 3.880s 477.366us 20 20 100.00
shadow_reg_update_error_with_csr_rw 18 20 90.00
clkmgr_shadow_reg_errors_with_csr_rw 7.750s 1283.044us 18 20 90.00
sec_cm_bus_integrity 25 25 100.00
clkmgr_tl_intg_err 4.650s 958.841us 25 25 100.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 15.920s 2483.197us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 18.520s 2183.803us 10 10 100.00
sec_cm_meas_config_shadow 20 20 100.00
clkmgr_shadow_reg_errors 3.880s 477.366us 20 20 100.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 2.800s 511.691us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 2.270s 316.680us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.350s 76.889us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_clk_handshake_intersig_mubi 1.350s 88.946us 10 10 100.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.430s 88.341us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.350s 77.578us 5 5 100.00
sec_cm_idle_ctr_redun 5 5 100.00
clkmgr_sec_cm 8.660s 2190.323us 5 5 100.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.350s 77.578us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.350s 77.578us 5 5 100.00
prim_count_check 5 5 100.00
clkmgr_sec_cm 8.660s 2190.323us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 9.420s 2598.744us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 62.360s 4452.695us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Write_and_check_update_error task: check storage_err status 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 67519507321780371821172406147361597127170228064159589115839149783063097186102 81
UVM_INFO @ 161451446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 63912522939159948311992826846958122684384986839697999597692709397188364503159 81
UVM_INFO @ 36025873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---