Simulation Results

Simulation Results: csrng

05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.91 %

code
96.24 %

assert
97.16 %

func
91.32 %

block
98.59 %

line
99.54 %

branch
96.55 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	13.000s	19.291us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	3.000s	22.517us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	3.000s	74.334us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	17.000s	335.682us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	2.000s	29.513us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	4.000s	57.905us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	3.000s	74.334us	5	5	100.00
	csrng_csr_aliasing	2.000s	29.513us	1	1	100.00

1307/1307 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	68.000s	3568.597us	500	500	100.00
err				500	500	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
cmds				25	25	100.00
	csrng_cmds	495.000s	33953.473us	25	25	100.00
life cycle				25	25	100.00
	csrng_cmds	495.000s	33953.473us	25	25	100.00
stress_all				25	25	100.00
	csrng_stress_all	1064.000s	50908.984us	25	25	100.00
intr_test				10	10	100.00
	csrng_intr_test	4.000s	121.458us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	5.000s	210.503us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	22.000s	541.859us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	22.000s	541.859us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	3.000s	22.517us	1	1	100.00
	csrng_csr_rw	3.000s	74.334us	5	5	100.00
	csrng_csr_aliasing	2.000s	29.513us	1	1	100.00
	csrng_same_csr_outstanding	5.000s	226.886us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	3.000s	22.517us	1	1	100.00
	csrng_csr_rw	3.000s	74.334us	5	5	100.00
	csrng_csr_aliasing	2.000s	29.513us	1	1	100.00
	csrng_same_csr_outstanding	5.000s	226.886us	5	5	100.00

V2S

1285/1285 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	6.000s	229.563us	5	5	100.00
	csrng_tl_intg_err	14.000s	312.732us	25	25	100.00
sec_cm_config_regwen				30	30	100.00
	csrng_regwen	9.000s	67.550us	25	25	100.00
	csrng_csr_rw	3.000s	74.334us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	68.000s	3568.597us	500	500	100.00
sec_cm_intersig_mubi				25	25	100.00
	csrng_stress_all	1064.000s	50908.984us	25	25	100.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
	csrng_sec_cm	6.000s	229.563us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
	csrng_sec_cm	6.000s	229.563us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
	csrng_sec_cm	6.000s	229.563us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
	csrng_sec_cm	6.000s	229.563us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
	csrng_sec_cm	6.000s	229.563us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	68.000s	3568.597us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
sec_cm_constants_lc_gated				25	25	100.00
	csrng_stress_all	1064.000s	50908.984us	25	25	100.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	68.000s	3568.597us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	14.000s	312.732us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
	csrng_sec_cm	6.000s	229.563us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00
	csrng_sec_cm	6.000s	229.563us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	27.000s	1597.682us	200	200	100.00
	csrng_err	36.000s	54.109us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	122.000s	3647.948us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done)				7 test runs
	csrng_stress_all_with_rand_reset	19836581492431604844968765365053309584686361659504791570727554961499710505127	138	UVM_INFO @ 54058352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	51403775033971500192887333975849609959812227227128201729558853717375920376705	111	UVM_INFO @ 31819561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	32680174043648113121623160188186205470025748443250730611757329732703557375622	105	UVM_INFO @ 5259141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	23541585888143393472719629318681534313567112213254012788007171385519416067053	105	UVM_INFO @ 5869219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	80583236720450871582930726372031304152783405067239693192507464640872844807659	201	UVM_INFO @ 3647947964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	14964190278850238972908909446111633875632853902433650706587562604836125967004	180	UVM_INFO @ 2430321645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	403630061424191838218112800602830028854321184047136619975580144601660810770	153	UVM_INFO @ 5046629555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:173) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				3 test runs
	csrng_stress_all_with_rand_reset	21152379881431085884160408355426559529311753544004467761222366456042257038818	110	UVM_INFO @ 631181619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	41542645749561618350375408489806772680184870272040741289091469577463910957445	139	UVM_INFO @ 1274773397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	86336160795885247181954248918159342221438178000453008943090957808148138181754	105	UVM_INFO @ 92821012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---