Simulation Results: edn/edn0

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.38 %
  • code
  • 94.99 %
  • assert
  • 98.48 %
  • func
  • 92.66 %
  • line
  • 98.86 %
  • branch
  • 96.23 %
  • cond
  • 93.56 %
  • toggle
  • 97.07 %
  • FSM
  • 89.25 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.57%
V3
96.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.390s 20.943us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.300s 32.517us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.320s 84.217us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.500s 336.241us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.360s 16.462us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.410s 59.697us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.320s 84.217us 5 5 100.00
edn_csr_aliasing 1.360s 16.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.000s 238.864us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.000s 238.864us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.000s 238.864us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.520s 22.036us 20 20 100.00
alerts 200 200 100.00
edn_alert 2.170s 255.107us 200 200 100.00
errs 100 100 100.00
edn_err 1.930s 50.149us 100 100 100.00
disable 100 100 100.00
edn_disable 1.390s 14.826us 50 50 100.00
edn_disable_auto_req_mode 1.940s 47.700us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 9.600s 425.403us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.260s 48.144us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.360s 20.474us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 6.220s 2340.625us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 6.220s 2340.625us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.300s 32.517us 1 1 100.00
edn_csr_rw 1.320s 84.217us 5 5 100.00
edn_csr_aliasing 1.360s 16.462us 1 1 100.00
edn_same_csr_outstanding 1.850s 106.909us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.300s 32.517us 1 1 100.00
edn_csr_rw 1.320s 84.217us 5 5 100.00
edn_csr_aliasing 1.360s 16.462us 1 1 100.00
edn_same_csr_outstanding 1.850s 106.909us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
edn_sec_cm 12.550s 632.764us 5 5 100.00
edn_tl_intg_err 3.380s 332.346us 24 25 96.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.290s 56.857us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 2.170s 255.107us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 12.550s 632.764us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 12.550s 632.764us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 12.550s 632.764us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 12.550s 632.764us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 2.170s 255.107us 200 200 100.00
edn_sec_cm 12.550s 632.764us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 2.170s 255.107us 200 200 100.00
sec_cm_tile_link_bus_integrity 24 25 96.00
edn_tl_intg_err 3.380s 332.346us 24 25 96.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 30 96.67
edn_stress_all_with_rand_reset 212.250s 14893.944us 29 30 96.67

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 69766745504258578149476655664254843321257816893236537146451522041069572363615 443
UVM_INFO @ 14893943507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [edn_common_vseq] Expected alert (fatal_alert) did not fire in * cycles. 1 test run
edn_tl_intg_err 13341651567601688162387821220509943124756346304745329596741528932064726339126 161
UVM_INFO @ 263990398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---