Simulation Results: edn/edn1

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.57 %
  • code
  • 96.09 %
  • assert
  • 98.18 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.69 %
  • toggle
  • 96.08 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.290s 18.657us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.220s 19.341us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.210s 101.878us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.310s 219.597us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.140s 29.718us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.970s 47.818us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.210s 101.878us 5 5 100.00
edn_csr_aliasing 1.140s 29.718us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.720s 324.233us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.720s 324.233us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.720s 324.233us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.410s 96.318us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.840s 195.622us 200 200 100.00
errs 100 100 100.00
edn_err 1.630s 27.677us 100 100 100.00
disable 100 100 100.00
edn_disable 1.260s 135.961us 50 50 100.00
edn_disable_auto_req_mode 1.730s 50.927us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 9.720s 483.647us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.170s 25.751us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.300s 25.259us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.810s 374.292us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.810s 374.292us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.220s 19.341us 1 1 100.00
edn_csr_rw 1.210s 101.878us 5 5 100.00
edn_csr_aliasing 1.140s 29.718us 1 1 100.00
edn_same_csr_outstanding 1.730s 68.556us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.220s 19.341us 1 1 100.00
edn_csr_rw 1.210s 101.878us 5 5 100.00
edn_csr_aliasing 1.140s 29.718us 1 1 100.00
edn_same_csr_outstanding 1.730s 68.556us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.140s 1344.030us 5 5 100.00
edn_tl_intg_err 3.460s 152.120us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.360s 19.467us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.840s 195.622us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.140s 1344.030us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.140s 1344.030us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.140s 1344.030us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.140s 1344.030us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.840s 195.622us 200 200 100.00
edn_sec_cm 7.140s 1344.030us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.840s 195.622us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.460s 152.120us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 30 100.00
edn_stress_all_with_rand_reset 125.800s 5763.494us 30 30 100.00