Simulation Results: hmac

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.14 %
  • code
  • 88.30 %
  • assert
  • 97.60 %
  • func
  • 99.52 %
  • line
  • 99.64 %
  • branch
  • 99.35 %
  • cond
  • 96.36 %
  • toggle
  • 46.17 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
97.14%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.570s 405.125us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.950s 29.701us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.160s 34.414us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.980s 664.175us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.380s 26.644us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 1.640s 32.569us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.160s 34.414us 5 5 100.00
hmac_csr_aliasing 1.380s 26.644us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 98.530s 24410.404us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 121.390s 18962.633us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 280.040s 31681.070us 30 30 100.00
hmac_test_sha384_vectors 575.580s 40536.594us 75 75 100.00
hmac_test_sha512_vectors 576.870s 43572.361us 75 75 100.00
hmac_test_hmac256_vectors 14.840s 1953.240us 50 50 100.00
hmac_test_hmac384_vectors 16.800s 2490.935us 60 60 100.00
hmac_test_hmac512_vectors 19.340s 575.427us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 44.480s 39867.058us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 2496.430s 18035.787us 10 10 100.00
error 10 10 100.00
hmac_error 147.050s 57146.770us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 209.950s 22726.757us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.570s 405.125us 10 10 100.00
hmac_long_msg 98.530s 24410.404us 10 10 100.00
hmac_back_pressure 121.390s 18962.633us 25 25 100.00
hmac_datapath_stress 2496.430s 18035.787us 10 10 100.00
hmac_burst_wr 44.480s 39867.058us 50 50 100.00
hmac_stress_all 5652.860s 35917.035us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.570s 405.125us 10 10 100.00
hmac_long_msg 98.530s 24410.404us 10 10 100.00
hmac_back_pressure 121.390s 18962.633us 25 25 100.00
hmac_datapath_stress 2496.430s 18035.787us 10 10 100.00
hmac_wipe_secret 209.950s 22726.757us 10 10 100.00
hmac_test_sha256_vectors 280.040s 31681.070us 30 30 100.00
hmac_test_sha384_vectors 575.580s 40536.594us 75 75 100.00
hmac_test_sha512_vectors 576.870s 43572.361us 75 75 100.00
hmac_test_hmac256_vectors 14.840s 1953.240us 50 50 100.00
hmac_test_hmac384_vectors 16.800s 2490.935us 60 60 100.00
hmac_test_hmac512_vectors 19.340s 575.427us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.570s 405.125us 10 10 100.00
hmac_long_msg 98.530s 24410.404us 10 10 100.00
hmac_back_pressure 121.390s 18962.633us 25 25 100.00
hmac_datapath_stress 2496.430s 18035.787us 10 10 100.00
hmac_burst_wr 44.480s 39867.058us 50 50 100.00
hmac_error 147.050s 57146.770us 10 10 100.00
hmac_wipe_secret 209.950s 22726.757us 10 10 100.00
hmac_test_sha256_vectors 280.040s 31681.070us 30 30 100.00
hmac_test_sha384_vectors 575.580s 40536.594us 75 75 100.00
hmac_test_sha512_vectors 576.870s 43572.361us 75 75 100.00
hmac_test_hmac256_vectors 14.840s 1953.240us 50 50 100.00
hmac_test_hmac384_vectors 16.800s 2490.935us 60 60 100.00
hmac_test_hmac512_vectors 19.340s 575.427us 75 75 100.00
hmac_stress_all 5652.860s 35917.035us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 5652.860s 35917.035us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.930s 43.822us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.960s 70.433us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 5.030s 3152.298us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 5.030s 3152.298us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 0.950s 29.701us 1 1 100.00
hmac_csr_rw 1.160s 34.414us 5 5 100.00
hmac_csr_aliasing 1.380s 26.644us 1 1 100.00
hmac_same_csr_outstanding 3.180s 152.721us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 0.950s 29.701us 1 1 100.00
hmac_csr_rw 1.160s 34.414us 5 5 100.00
hmac_csr_aliasing 1.380s 26.644us 1 1 100.00
hmac_same_csr_outstanding 3.180s 152.721us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.430s 202.259us 5 5 100.00
hmac_tl_intg_err 4.840s 340.670us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 4.840s 340.670us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.570s 405.125us 10 10 100.00
stress_reset 24 25 96.00
hmac_stress_reset 5.890s 128.585us 24 25 96.00
stress_all_with_rand_reset 34 35 97.14
hmac_stress_all_with_rand_reset 432.060s 28446.668us 34 35 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.060s 184.148us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [hmac_common_vseq] wait timeout occurred! 1 test run
hmac_stress_all_with_rand_reset 11545866416034099508318912986108240729850608980566467810486579886791935834722 12376
UVM_INFO @ 40972091370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [hmac_stress_reset_vseq] wait timeout occurred! 1 test run
hmac_stress_reset 92432860127441387163578613642540747638223559598845291033090065862972736080312 166
UVM_INFO @ 10140483248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---