Simulation Results: lc_ctrl/volatile_unlock_disabled

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.31 %
  • code
  • 85.89 %
  • assert
  • 94.97 %
  • func
  • 96.06 %
  • line
  • 97.28 %
  • branch
  • 93.90 %
  • cond
  • 81.70 %
  • toggle
  • 88.33 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
94.85%
V2S
97.33%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.170s 485.900us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.170s 46.291us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.290s 35.421us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.530s 75.777us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.310s 287.343us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.460s 215.510us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.290s 35.421us 5 5 100.00
lc_ctrl_csr_aliasing 1.310s 287.343us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.620s 131.727us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 13.790s 1262.894us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.190s 13.929us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.390s 337.046us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 12.930s 389.726us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 10.090s 2415.856us 19 20 95.00
security_escalation 126 140 90.00
lc_ctrl_state_failure 12.930s 389.726us 20 20 100.00
lc_ctrl_prog_failure 3.390s 337.046us 20 20 100.00
lc_ctrl_errors 10.090s 2415.856us 19 20 95.00
lc_ctrl_security_escalation 11.510s 590.125us 20 20 100.00
lc_ctrl_jtag_state_failure 47.050s 2958.184us 13 20 65.00
lc_ctrl_jtag_prog_failure 13.850s 1506.340us 17 20 85.00
lc_ctrl_jtag_errors 55.270s 7708.725us 17 20 85.00
jtag_access 200 210 95.24
lc_ctrl_jtag_smoke 14.400s 13979.053us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.880s 1104.505us 16 20 80.00
lc_ctrl_jtag_prog_failure 13.850s 1506.340us 17 20 85.00
lc_ctrl_jtag_errors 55.270s 7708.725us 17 20 85.00
lc_ctrl_jtag_access 12.520s 7454.134us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 26.290s 1262.134us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.560s 185.261us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 735.116us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 20.300s 1992.965us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 3.360s 379.971us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.640s 140.859us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.050s 1198.416us 10 10 100.00
lc_ctrl_jtag_alert_test 2.450s 548.038us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 40.360s 13728.144us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.350s 36.049us 10 10 100.00
stress_all 6 10 60.00
lc_ctrl_stress_all 316.050s 70898.612us 6 10 60.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.380s 407.682us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.310s 513.054us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.310s 513.054us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.170s 46.291us 1 1 100.00
lc_ctrl_csr_rw 1.290s 35.421us 5 5 100.00
lc_ctrl_csr_aliasing 1.310s 287.343us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.840s 434.063us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.170s 46.291us 1 1 100.00
lc_ctrl_csr_rw 1.290s 35.421us 5 5 100.00
lc_ctrl_csr_aliasing 1.310s 287.343us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.840s 434.063us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.040s 1418.864us 5 5 100.00
lc_ctrl_tl_intg_err 3.240s 126.155us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.240s 126.155us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 13.790s 1262.894us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 12.930s 389.726us 20 20 100.00
lc_ctrl_sec_cm 10.040s 1418.864us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 12.930s 389.726us 20 20 100.00
lc_ctrl_sec_cm 10.040s 1418.864us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.930s 389.726us 20 20 100.00
lc_ctrl_sec_cm 10.040s 1418.864us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.930s 389.726us 20 20 100.00
lc_ctrl_sec_cm 10.040s 1418.864us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 12.930s 389.726us 20 20 100.00
lc_ctrl_sec_cm 10.040s 1418.864us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.930s 389.726us 20 20 100.00
lc_ctrl_sec_cm 10.040s 1418.864us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.930s 389.726us 20 20 100.00
lc_ctrl_sec_cm 10.040s 1418.864us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 12.930s 389.726us 20 20 100.00
lc_ctrl_sec_cm 10.040s 1418.864us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 11.510s 590.125us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 36 40 90.00
lc_ctrl_state_post_trans 9.620s 131.727us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.880s 1104.505us 16 20 80.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.860s 482.913us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.860s 482.913us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.410s 1226.858us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.490s 851.462us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.490s 851.462us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
lc_ctrl_stress_all_with_rand_reset 93.930s 9203.539us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 18 test runs
lc_ctrl_stress_all_with_rand_reset 82732941195005838228022962288960832436500030847178208349001401630034142567956 5624
UVM_INFO @ 919013664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 59620771670965167359890170811239002994023720194706085329708192644767931870883 1140
UVM_INFO @ 3745676297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 30322593786484188199499800123424258309084448728969347830682277562487055651634 529
UVM_INFO @ 1530420156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 77311539613307468208119534072077299614738698596733999392520696043129880546570 5820
UVM_INFO @ 8884670228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 30718608412058733115810486262567566980574143973349021567338301424181934786102 209
UVM_INFO @ 102573610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50203841432375794701002241412070597310958516876222584002582925582215379980922 292
UVM_INFO @ 18385519584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 65009950680304274388152976971596776462080832433999418788963092929319629741294 1368
UVM_INFO @ 1997992207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 75020394930327139918456409275899457821438583771697730462135355649722506052070 1301
UVM_INFO @ 758798391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 71577756279627029653280676352320362740031006162921592535825652513288673966589 509
UVM_INFO @ 2635453570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 44248927379662214991367163747268643888144425425707943131690216410786979721775 7374
UVM_INFO @ 37989146989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 23098757239466617798484451544972352214211290844045902030331262417087523988726 1078
UVM_INFO @ 1486266908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 71747553938243324405083671204915003493778237306312122001540298472287594363031 438
UVM_INFO @ 1592562406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 35339192755717044776915182571839864727953471579146897681960033759529926880959 483
UVM_INFO @ 492433103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 112872678849230218185510854509615977673504693028139774639922508273747294711298 910
UVM_INFO @ 435546970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 23262068360591779847429303063508207498731037929185370523145083132586563739725 211
UVM_INFO @ 73751550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 28656732647937917462061998020788163439167027663037097230978888705886031961771 614
UVM_INFO @ 302368167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 15892981256178482410397174553133117930739310373519680536758252367216489199485 392
UVM_INFO @ 573143277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 18985443445563129280738835003096718767855107433035909489163091047484295943517 209
UVM_INFO @ 180916746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 6 test runs
lc_ctrl_jtag_errors 67493657666593092265419787590924124087362577446683419847333651171080136134211 3061
UVM_INFO @ 7708725388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 95023968480965158259533345687751846682396097849459354305515941957423559738785 5739
UVM_INFO @ 1169716599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 64832398196019392106221377248619056509266103399079906500798488187464150869046 463
UVM_INFO @ 2593264873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 101292250914533187994601112309400939214340590633010661025864990408888202951795 459
UVM_INFO @ 570802869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 3645820840426098112064951858689970293794427812642792414843526669437258851105 249
UVM_INFO @ 288780358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 28050644993625550740260217433796442389438238644735782443331363122832903135857 295
UVM_INFO @ 1033071555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 3 test runs
lc_ctrl_errors 51792982141214266363539119275791786178374554404452757294467163019126261915127 1578
UVM_INFO @ 153838773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 89168021976633316751165209540453616895621564229645785777876634798027510975226 3759
UVM_INFO @ 6494942794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48051162938213014605426392067120496608304361657062972059598588921420157841490 2544
UVM_INFO @ 1233826967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
lc_ctrl_stress_all_with_rand_reset 61622398140379077993379392807138843275091840661551153340249178961782439419662 6847
UVM_INFO @ 3038816702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 114944473749879037119504386402720575336820645212719762775562470007179234656637 15865
UVM_INFO @ 15627149552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---