Simulation Results: lc_ctrl/volatile_unlock_enabled

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.22 %
  • code
  • 85.76 %
  • assert
  • 94.83 %
  • func
  • 96.06 %
  • line
  • 97.26 %
  • branch
  • 94.00 %
  • cond
  • 81.90 %
  • toggle
  • 88.33 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
94.61%
V2S
98.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.170s 129.648us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.230s 32.187us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.200s 15.997us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.670s 140.480us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.320s 19.618us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.540s 32.998us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.200s 15.997us 5 5 100.00
lc_ctrl_csr_aliasing 1.320s 19.618us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 8.060s 79.357us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 14.500s 1384.517us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.210s 22.687us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 2.840s 117.261us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 12.980s 369.542us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 12.980s 2891.905us 19 20 95.00
security_escalation 123 140 87.86
lc_ctrl_state_failure 12.980s 369.542us 20 20 100.00
lc_ctrl_prog_failure 2.840s 117.261us 20 20 100.00
lc_ctrl_errors 12.980s 2891.905us 19 20 95.00
lc_ctrl_security_escalation 7.950s 337.498us 20 20 100.00
lc_ctrl_jtag_state_failure 60.490s 46750.761us 12 20 60.00
lc_ctrl_jtag_prog_failure 12.760s 4122.318us 16 20 80.00
lc_ctrl_jtag_errors 48.880s 11898.373us 16 20 80.00
jtag_access 199 210 94.76
lc_ctrl_jtag_smoke 7.360s 1456.888us 20 20 100.00
lc_ctrl_jtag_state_post_trans 19.560s 1204.680us 17 20 85.00
lc_ctrl_jtag_prog_failure 12.760s 4122.318us 16 20 80.00
lc_ctrl_jtag_errors 48.880s 11898.373us 16 20 80.00
lc_ctrl_jtag_access 13.240s 4440.777us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 23.250s 12144.486us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.810s 2476.146us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.550s 179.167us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 17.660s 9850.150us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 3.840s 206.049us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.930s 83.888us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.070s 414.608us 10 10 100.00
lc_ctrl_jtag_alert_test 2.200s 102.250us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 14.070s 5672.062us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.650s 20.735us 10 10 100.00
stress_all 7 10 70.00
lc_ctrl_stress_all 250.070s 90083.060us 7 10 70.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.390s 30.240us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 3.700s 275.680us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 3.700s 275.680us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.230s 32.187us 1 1 100.00
lc_ctrl_csr_rw 1.200s 15.997us 5 5 100.00
lc_ctrl_csr_aliasing 1.320s 19.618us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.700s 46.439us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.230s 32.187us 1 1 100.00
lc_ctrl_csr_rw 1.200s 15.997us 5 5 100.00
lc_ctrl_csr_aliasing 1.320s 19.618us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.700s 46.439us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.170s 221.217us 5 5 100.00
lc_ctrl_tl_intg_err 3.010s 640.200us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.010s 640.200us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 14.500s 1384.517us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 12.980s 369.542us 20 20 100.00
lc_ctrl_sec_cm 9.170s 221.217us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 12.980s 369.542us 20 20 100.00
lc_ctrl_sec_cm 9.170s 221.217us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.980s 369.542us 20 20 100.00
lc_ctrl_sec_cm 9.170s 221.217us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.980s 369.542us 20 20 100.00
lc_ctrl_sec_cm 9.170s 221.217us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 12.980s 369.542us 20 20 100.00
lc_ctrl_sec_cm 9.170s 221.217us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.980s 369.542us 20 20 100.00
lc_ctrl_sec_cm 9.170s 221.217us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.980s 369.542us 20 20 100.00
lc_ctrl_sec_cm 9.170s 221.217us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 12.980s 369.542us 20 20 100.00
lc_ctrl_sec_cm 9.170s 221.217us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 7.950s 337.498us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 37 40 92.50
lc_ctrl_state_post_trans 8.060s 79.357us 20 20 100.00
lc_ctrl_jtag_state_post_trans 19.560s 1204.680us 17 20 85.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.540s 1094.309us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.540s 1094.309us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.680s 3274.328us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.240s 3167.287us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.240s 3167.287us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 71.830s 25524.704us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 13 test runs
lc_ctrl_jtag_state_failure 24573522683666837343208034263512889711655581832130441164562611265390126992314 1317
UVM_INFO @ 5187742246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 49522910600115514445840978061685449455724290699753008646706460100405424049196 346
UVM_INFO @ 412170815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 67196554004365922827100414100581974275688241036326485463517382335890353172087 518
UVM_INFO @ 456533718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 54073776820188553984341519052794981116532944050233446279099822432219609689637 2119
UVM_INFO @ 6528253505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98496718591255548897067959636724291902706660352234470084439085408465771597956 10724
UVM_INFO @ 3808827039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 92023128029408910228670923540070999262655999168786066976133190311063375481403 395
UVM_INFO @ 443579238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 102773537755630611625720813492984525418505704872161880717458187375164597248835 2670
UVM_INFO @ 2884186606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 104215450498753422981761804082793049143940547773512602530463074309600342630042 594
UVM_INFO @ 135973210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 110838451503628475081880480377942449397459960826053690498628386690638408986032 628
UVM_INFO @ 400634629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 21180429221120298193192298176367535747762511500062681929724104675231490212934 257
UVM_INFO @ 188176425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 68501703223986462761298154343766102385067257639767881996061360797258342313749 212
UVM_INFO @ 86687654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 69317130926445778188477563433545870519165900313171854924275821094452089485320 445
UVM_INFO @ 335828811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 65713557416877226392277111686820936155087321723396879331139131353203728958745 212
UVM_INFO @ 151952525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 11 test runs
lc_ctrl_jtag_errors 51908862970722688146474357696494587972206223356832203487725520393636523256814 2379
UVM_INFO @ 1956396484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 62775085577798984313121542264861923502004573938943054523734734551752689783858 251
UVM_INFO @ 1374121655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 50822018531363117033560243757463976685108635124909391450039227932772137728589 955
UVM_INFO @ 733404376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 13706443785109958648482285252579192590508911112150270019979705262812456567411 294
UVM_INFO @ 808189151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 113158249860940824929205156124475189480298646416257260972727268118504902196899 334
UVM_INFO @ 412550203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 56912715988342918773315868354745976363045593579467186176035336793291987826213 2923
UVM_INFO @ 4457102652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1790673848634921864056288537627395895643237641288869206048089515228676149342 5180
UVM_INFO @ 2666188850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 97874536531372084606610052853874544732190102721826929655801690602671066142786 504
UVM_INFO @ 1582627752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 72947912895668695741643560932089024644740638000346251958468819290754834582943 378
UVM_INFO @ 299555991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 656559475954705020826382020276382935267540844165233254733340769062128829611 463
UVM_INFO @ 150461719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 41969167072184317075558891528544607538637041866353528479346083888184960580339 3539
UVM_INFO @ 15975706155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_stress_all_with_rand_reset 92752816689272692518045999435000970854522951292538458357400300977936418332409 2269
UVM_INFO @ 1615839460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 41677528904910533677809758889316240008064127007775921211404011339484105699131 957
UVM_INFO @ 70000130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
lc_ctrl_stress_all_with_rand_reset 8208365468696694202128776921151801581847507621264655647625296738457399674219 1713
UVM_INFO @ 6502860097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24390445623469389496225671692555629886345420463838129432346953041284221321614 181
UVM_INFO @ 1834848145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:933) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 102809476894681403884481486297683787861854507267933906751307209409512612200850 1393
UVM_INFO @ 8956245257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---