| V1 |
|
100.00% |
| V2 |
|
97.06% |
| V2S |
|
97.26% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| otbn_smoke | 16.000s | 39.476us | 1 | 1 | 100.00 | |
| otbn_smoke_vectorized | 10.000s | 19.297us | 1 | 1 | 100.00 | |
| single_binary | 100 | 100 | 100.00 | |||
| otbn_single | 47.000s | 219.519us | 100 | 100 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 6.000s | 18.871us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| otbn_csr_rw | 6.000s | 61.790us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 10.000s | 141.924us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 5.000s | 46.290us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 11.000s | 69.925us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| otbn_csr_rw | 6.000s | 61.790us | 5 | 5 | 100.00 | |
| otbn_csr_aliasing | 5.000s | 46.290us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 97.000s | 935.597us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 58.000s | 1356.224us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 10 | 10 | 100.00 | |||
| otbn_reset | 68.000s | 139.908us | 10 | 10 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 84.000s | 474.063us | 1 | 1 | 100.00 | |
| wfi | 4 | 7 | 57.14 | |||
| otbn_wfi_smoke | 7.000s | 9.343us | 0 | 1 | 0.00 | |
| otbn_wfi_sec_wipe | 17.000s | 44.886us | 4 | 5 | 80.00 | |
| otbn_wfi_back_to_back | 7.000s | 4.264us | 0 | 1 | 0.00 | |
| back_to_back | 9 | 10 | 90.00 | |||
| otbn_multi | 3602.090s | 0.000us | 9 | 10 | 90.00 | |
| stress_all | 10 | 10 | 100.00 | |||
| otbn_stress_all | 215.000s | 780.832us | 10 | 10 | 100.00 | |
| lc_escalation | 59 | 60 | 98.33 | |||
| otbn_escalate | 85.000s | 1329.189us | 59 | 60 | 98.33 | |
| zero_state_err_urnd | 5 | 5 | 100.00 | |||
| otbn_zero_state_err_urnd | 12.000s | 19.451us | 5 | 5 | 100.00 | |
| sw_errs_fatal_chk | 10 | 10 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 23.000s | 22.362us | 10 | 10 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| otbn_alert_test | 12.000s | 334.310us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| otbn_intr_test | 5.000s | 15.104us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| otbn_tl_errors | 12.000s | 911.690us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| otbn_tl_errors | 12.000s | 911.690us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| otbn_csr_hw_reset | 6.000s | 18.871us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 6.000s | 61.790us | 5 | 5 | 100.00 | |
| otbn_csr_aliasing | 5.000s | 46.290us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 7.000s | 26.621us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| otbn_csr_hw_reset | 6.000s | 18.871us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 6.000s | 61.790us | 5 | 5 | 100.00 | |
| otbn_csr_aliasing | 5.000s | 46.290us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 7.000s | 26.621us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 24 | 25 | 96.00 | |||
| otbn_imem_err | 55.000s | 131.919us | 9 | 10 | 90.00 | |
| otbn_dmem_err | 17.000s | 28.278us | 15 | 15 | 100.00 | |
| internal_integrity | 14 | 17 | 82.35 | |||
| otbn_alu_bignum_mod_err | 17.000s | 118.111us | 4 | 5 | 80.00 | |
| otbn_controller_ispr_rdata_err | 20.000s | 43.343us | 5 | 5 | 100.00 | |
| otbn_mac_bignum_acc_err | 15.000s | 56.525us | 4 | 5 | 80.00 | |
| otbn_urnd_err | 11.000s | 49.343us | 1 | 2 | 50.00 | |
| illegal_bus_access | 5 | 5 | 100.00 | |||
| otbn_illegal_mem_acc | 13.000s | 40.869us | 5 | 5 | 100.00 | |
| otbn_mem_gnt_acc_err | 2 | 2 | 100.00 | |||
| otbn_mem_gnt_acc_err | 11.000s | 20.410us | 2 | 2 | 100.00 | |
| otbn_non_sec_partial_wipe | 9 | 10 | 90.00 | |||
| otbn_partial_wipe | 11.000s | 27.066us | 9 | 10 | 90.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| otbn_tl_intg_err | 130.000s | 792.702us | 25 | 25 | 100.00 | |
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 115.000s | 364.803us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 16.000s | 39.476us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 15 | 15 | 100.00 | |||
| otbn_dmem_err | 17.000s | 28.278us | 15 | 15 | 100.00 | |
| sec_cm_instruction_mem_integrity | 9 | 10 | 90.00 | |||
| otbn_imem_err | 55.000s | 131.919us | 9 | 10 | 90.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| otbn_tl_intg_err | 130.000s | 792.702us | 25 | 25 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 59 | 60 | 98.33 | |||
| otbn_escalate | 85.000s | 1329.189us | 59 | 60 | 98.33 | |
| sec_cm_controller_fsm_local_esc | 39 | 40 | 97.50 | |||
| otbn_imem_err | 55.000s | 131.919us | 9 | 10 | 90.00 | |
| otbn_dmem_err | 17.000s | 28.278us | 15 | 15 | 100.00 | |
| otbn_zero_state_err_urnd | 12.000s | 19.451us | 5 | 5 | 100.00 | |
| otbn_illegal_mem_acc | 13.000s | 40.869us | 5 | 5 | 100.00 | |
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_controller_fsm_sparse | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 100 | 100 | 100.00 | |||
| otbn_single | 47.000s | 219.519us | 100 | 100 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 39 | 40 | 97.50 | |||
| otbn_imem_err | 55.000s | 131.919us | 9 | 10 | 90.00 | |
| otbn_dmem_err | 17.000s | 28.278us | 15 | 15 | 100.00 | |
| otbn_zero_state_err_urnd | 12.000s | 19.451us | 5 | 5 | 100.00 | |
| otbn_illegal_mem_acc | 13.000s | 40.869us | 5 | 5 | 100.00 | |
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 59 | 60 | 98.33 | |||
| otbn_escalate | 85.000s | 1329.189us | 59 | 60 | 98.33 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 39 | 40 | 97.50 | |||
| otbn_imem_err | 55.000s | 131.919us | 9 | 10 | 90.00 | |
| otbn_dmem_err | 17.000s | 28.278us | 15 | 15 | 100.00 | |
| otbn_zero_state_err_urnd | 12.000s | 19.451us | 5 | 5 | 100.00 | |
| otbn_illegal_mem_acc | 13.000s | 40.869us | 5 | 5 | 100.00 | |
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_data_reg_sw_sca | 100 | 100 | 100.00 | |||
| otbn_single | 47.000s | 219.519us | 100 | 100 | 100.00 | |
| sec_cm_ctrl_redun | 12 | 12 | 100.00 | |||
| otbn_ctrl_redun | 15.000s | 27.728us | 12 | 12 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 5 | 5 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 14.000s | 56.550us | 5 | 5 | 100.00 | |
| sec_cm_rnd_bus_consistency | 5 | 5 | 100.00 | |||
| otbn_rnd_sec_cm | 118.000s | 2126.600us | 5 | 5 | 100.00 | |
| sec_cm_rnd_rng_digest | 5 | 5 | 100.00 | |||
| otbn_rnd_sec_cm | 118.000s | 2126.600us | 5 | 5 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 10 | 10 | 100.00 | |||
| otbn_rf_base_intg_err | 18.000s | 41.876us | 10 | 10 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 9 | 10 | 90.00 | |||
| otbn_rf_bignum_intg_err | 15.000s | 129.131us | 9 | 10 | 90.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_loop_stack_ctr_redun | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| sec_cm_loop_stack_addr_integrity | 4 | 5 | 80.00 | |||
| otbn_stack_addr_integ_chk | 16.000s | 62.347us | 4 | 5 | 80.00 | |
| sec_cm_call_stack_addr_integrity | 4 | 5 | 80.00 | |||
| otbn_stack_addr_integ_chk | 16.000s | 62.347us | 4 | 5 | 80.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 7 | 7 | 100.00 | |||
| otbn_sec_wipe_err | 18.000s | 24.262us | 7 | 7 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 100 | 100 | 100.00 | |||
| otbn_single | 47.000s | 219.519us | 100 | 100 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 100 | 100 | 100.00 | |||
| otbn_single | 47.000s | 219.519us | 100 | 100 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 100 | 100 | 100.00 | |||
| otbn_single | 47.000s | 219.519us | 100 | 100 | 100.00 | |
| sec_cm_write_mem_integrity | 9 | 10 | 90.00 | |||
| otbn_multi | 3602.090s | 0.000us | 9 | 10 | 90.00 | |
| sec_cm_ctrl_flow_count | 100 | 100 | 100.00 | |||
| otbn_single | 47.000s | 219.519us | 100 | 100 | 100.00 | |
| sec_cm_ctrl_flow_sca | 100 | 100 | 100.00 | |||
| otbn_single | 47.000s | 219.519us | 100 | 100 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 5 | 5 | 100.00 | |||
| otbn_sw_no_acc | 26.000s | 74.727us | 5 | 5 | 100.00 | |
| sec_cm_key_sideload | 100 | 100 | 100.00 | |||
| otbn_single | 47.000s | 219.519us | 100 | 100 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 585.000s | 3181.350us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| otbn_stress_all_with_rand_reset | 305.000s | 3398.101us | 0 | 10 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 8 test runs | |||
| otbn_stress_all_with_rand_reset | 62593253935026985852973503158215416511545168611896429984622169184881872482221 | 160 |
UVM_INFO @ 251463491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 46592423610001222571915716459904329432418626064877601976561184193362288175021 | 150 |
UVM_INFO @ 91411141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 63280875741078887035008920566562969678424502268404140097225381835479554610217 | 150 |
UVM_INFO @ 9466653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 16278787645412130371402413955089814132091852594608409169630320973873678573418 | 162 |
UVM_INFO @ 124352577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 42418885040729673767520961780709467134124607717670190347606848471699370608408 | 147 |
UVM_INFO @ 21305286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 18123845164898022948443178194819289368031097655804154766188384098331285451527 | 151 |
UVM_INFO @ 18864090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 57127456568760581349212459533976554470657410031494382232275432384548622770818 | 150 |
UVM_INFO @ 10038083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 52478354430027015196748168940525927070531276729451054218062062841422674793196 | 185 |
UVM_INFO @ 247180726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error | 4 test runs | |||
| otbn_imem_err | 52695794592433024058815518894938260695896293421997142846014327448203469301883 | 107 |
UVM_INFO @ 13458970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_alu_bignum_mod_err | 15453556141549147254972277602103579050480152863048464693993397946555226022095 | 129 |
UVM_INFO @ 13169747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_mac_bignum_acc_err | 44865787381692431159248139711224868836769716216071898680009352561540545300014 | 122 |
UVM_INFO @ 147869835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_rf_bignum_intg_err | 95092326805145973515413047587927690466114076060218271244707093623486977249704 | 109 |
UVM_INFO @ 78440224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [*] vs * [*]) Saw instruction when not in BUSY_EXECUTE operational state. | 2 test runs | |||
| otbn_wfi_smoke | 30867461528509020804152668060018646580791946819066968375061842170207694380169 | 111 |
UVM_INFO @ 9343497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_wfi_back_to_back | 83957812779329285973564453569697712386483419935342520417658259720987807657670 | 111 |
UVM_INFO @ 4264002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 2 test runs | |||
| otbn_stress_all_with_rand_reset | 33880138817030361032628505162776673908843605844634529021178822783184570883889 | 183 |
UVM_INFO @ 3398101141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 100506445088170565581841127242084523228061806224602817602574748567543638315401 | 222 |
UVM_INFO @ 325276092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed | 1 test run | |||
| otbn_stack_addr_integ_chk | 113425693628823062528210077923795617660649668293394049748953382904899099903767 | 120 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,158): (time 19434213 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 19434213 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 19434213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value. | 1 test run | |||
| otbn_wfi_sec_wipe | 24195220415258379633870037402813079100144161397934575954980019956529749499240 | 111 |
UVM_FATAL @ 4688860 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 4688860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed | 1 test run | |||
| otbn_urnd_err | 87799911202173540722702738931106879581035895999682573606120272985097095340671 | 115 |
UVM_ERROR @ 49342578 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 49342578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 1 test run | |||
| otbn_multi | 103393780928942844796965676401674479603675257065637676764295142432287171843461 | None | ||
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,186): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS) | 1 test run | |||
| otbn_partial_wipe | 103095331477208199756780744700006417655381946055321864116755474542366447547516 | 126 |
UVM_ERROR @ 6619957 ps: (otbn_idle_checker.sv:186) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A
UVM_INFO @ 6619957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status | 1 test run | |||
| otbn_escalate | 18272669567779438796275566960262760006606543681774969315112312375840820076054 | 105 |
UVM_INFO @ 4587813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|