Simulation Results: otp_ctrl

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.63 %
  • code
  • 85.30 %
  • assert
  • 95.47 %
  • func
  • 91.11 %
  • line
  • 90.18 %
  • branch
  • 86.61 %
  • cond
  • 93.93 %
  • toggle
  • 92.57 %
  • FSM
  • 63.19 %
Validation stages
V1
100.00%
V2
74.37%
V2S
74.09%
V3
21.78%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.180s 110.406us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 13.070s 3649.180us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.040s 98.437us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.340s 64.055us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 10.840s 1161.334us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.460s 891.326us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 6.060s 1617.764us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.340s 64.055us 5 5 100.00
otp_ctrl_csr_aliasing 3.460s 891.326us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.530s 101.956us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.690s 42.453us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 48.220s 14815.179us 1 1 100.00
init_fail 246 300 82.00
otp_ctrl_init_fail 8.140s 2392.039us 246 300 82.00
partition_check 22 60 36.67
otp_ctrl_background_chks 45.040s 20488.446us 6 10 60.00
otp_ctrl_check_fail 60.190s 19515.338us 16 50 32.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 15.640s 4763.077us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 126.010s 39723.423us 30 30 100.00
interface_key_check 8 10 80.00
otp_ctrl_parallel_key_req 34.990s 4467.322us 8 10 80.00
lc_interactions 145 210 69.05
otp_ctrl_parallel_lc_req 31.510s 1820.814us 10 10 100.00
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
otp_dai_errors 7 25 28.00
otp_ctrl_dai_errs 35.100s 3705.244us 7 25 28.00
otp_macro_errors 1 10 10.00
otp_ctrl_macro_errs 12.340s 2814.861us 1 10 10.00
test_access 10 10 100.00
otp_ctrl_test_access 36.770s 4248.562us 10 10 100.00
stress_all 3 10 30.00
otp_ctrl_stress_all 182.910s 81274.810us 3 10 30.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.500s 612.485us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 2.890s 193.539us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 11.410s 2729.624us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 11.410s 2729.624us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 3.040s 98.437us 1 1 100.00
otp_ctrl_csr_rw 2.340s 64.055us 5 5 100.00
otp_ctrl_csr_aliasing 3.460s 891.326us 1 1 100.00
otp_ctrl_same_csr_outstanding 8.760s 1743.873us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 3.040s 98.437us 1 1 100.00
otp_ctrl_csr_rw 2.340s 64.055us 5 5 100.00
otp_ctrl_csr_aliasing 3.460s 891.326us 1 1 100.00
otp_ctrl_same_csr_outstanding 8.760s 1743.873us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
tl_intg_err 21 30 70.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
otp_ctrl_tl_intg_err 31.310s 8422.448us 17 25 68.00
prim_count_check 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
prim_fsm_check 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_bus_integrity 17 25 68.00
otp_ctrl_tl_intg_err 31.310s 8422.448us 17 25 68.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 13.070s 3649.180us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 13.070s 3649.180us 10 10 100.00
sec_cm_dai_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_kdi_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_lci_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_part_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_scrmbl_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_timer_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_dai_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_kdi_seed_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_kdi_entropy_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_lci_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_part_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_scrmbl_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_timer_integ_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_timer_cnsty_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_timer_lfsr_redun 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_dai_fsm_local_esc 139 205 67.80
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_lci_fsm_local_esc 135 200 67.50
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
sec_cm_kdi_fsm_local_esc 135 200 67.50
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
sec_cm_part_fsm_local_esc 136 210 64.76
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
otp_ctrl_macro_errs 12.340s 2814.861us 1 10 10.00
sec_cm_scrmbl_fsm_local_esc 135 200 67.50
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
sec_cm_timer_fsm_local_esc 139 205 67.80
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_dai_fsm_global_esc 139 205 67.80
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_lci_fsm_global_esc 135 200 67.50
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
sec_cm_kdi_fsm_global_esc 135 200 67.50
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
sec_cm_part_fsm_global_esc 136 210 64.76
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
otp_ctrl_macro_errs 12.340s 2814.861us 1 10 10.00
sec_cm_scrmbl_fsm_global_esc 135 200 67.50
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
sec_cm_timer_fsm_global_esc 139 205 67.80
otp_ctrl_parallel_lc_esc 34.510s 17880.687us 135 200 67.50
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_part_data_reg_integrity 246 300 82.00
otp_ctrl_init_fail 8.140s 2392.039us 246 300 82.00
sec_cm_part_data_reg_bkgn_chk 16 50 32.00
otp_ctrl_check_fail 60.190s 19515.338us 16 50 32.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 126.010s 39723.423us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 126.010s 39723.423us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 126.010s 39723.423us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 126.010s 39723.423us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 126.010s 39723.423us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 13.070s 3649.180us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 126.010s 39723.423us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 13.070s 3649.180us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 235.910s 43524.796us 4 5 80.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 15.640s 4763.077us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 13.070s 3649.180us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 13.070s 3649.180us 10 10 100.00
sec_cm_macro_mem_integrity 1 10 10.00
otp_ctrl_macro_errs 12.340s 2814.861us 1 10 10.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.790s 3576.359us 1 1 100.00
stress_all_with_rand_reset 21 100 21.00
otp_ctrl_stress_all_with_rand_reset 3600.145s 0.000us 21 100 21.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 70 test runs
otp_ctrl_dai_errs 107574307664596378184698067111085151840412663512690973476991728915176826160784 3139
UVM_INFO @ 1335437551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 82680769523072451299757583889007473026074117164744389091975834044400423726092 18386
UVM_INFO @ 714277978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 5194897020444239416628456960470170650682484131585311237693418749329436080461 7151
UVM_INFO @ 521487626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23967807504476336126321649319035085525601246704523539809318295647501725082788 2115
UVM_INFO @ 864822133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 56411292266677482695795398532011650507903548687167998814993305430370996929505 1115
UVM_INFO @ 276630848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 111559870332984629136946476845668099692976280418369463068634895877481920532100 4471
UVM_INFO @ 673033286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 96686599962705879463583842901682756520942090885505673063048376284737672144065 1720
UVM_INFO @ 273110836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 69504234442756350437540510375962228879268046769200498600767270379104056040578 1970
UVM_INFO @ 2977267417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36803674622730938761080169266549173479516582288516405226449032710246478377385 853
UVM_INFO @ 2167067134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 74570467027175171227859702783445546776403450615000919278037288301648005896251 87470
UVM_INFO @ 16503617547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 50440153015102244046343067593593241858092568904651673508736298065079465668297 10602
UVM_INFO @ 691018012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 7876848839849415577716793114801131139512865717438562798509892626388248980708 2651
UVM_INFO @ 982984016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 24986968061585075508419121113340560398110339944026059671984615210909241564924 3074
UVM_INFO @ 613533164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 55840978601221417482380363791633545338941767108447885488387306695369031491541 3939
UVM_INFO @ 5116319018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 104718328668113929537047243122997887873973433498517199900759523377181668000620 11047
UVM_INFO @ 807346422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 30507941838614342425103019396066956524747656926193771661646568856796574103540 2364
UVM_INFO @ 168537647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 68359210076803970371220635705371435851617691358181874063519548651314282439545 2045
UVM_INFO @ 2684574424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47958465316062949898682600066107798621758396622630251760637626101696384544503 10991
UVM_INFO @ 55372462064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 74811784127219269170379616396547904771824101041962500468852425292775272344455 2130
UVM_INFO @ 319149614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 31520980038442469860884551699186962880308298425394824553490796715742883675108 5873
UVM_INFO @ 13536990666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78394985738249275801702635804644130460549341999265898256790589746570227849282 14501
UVM_INFO @ 20298482036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 93979511998037831809812189889451833800375221424483220585911572077402850605064 1363
UVM_INFO @ 131434676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 100311718448774482465806072763906922395288805959011073677322274053204034827114 1058
UVM_INFO @ 82560770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56694445701324068748440981880140523765612057713462111777908673610391511488531 55792
UVM_INFO @ 66055731500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 82663765405595589697144273948087648049450483734860790425768953780517697308141 1227
UVM_INFO @ 46328603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 86111350783899145590790858678721664368795187708682628633978960581775135318121 8218
UVM_INFO @ 518496337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 82000444879245535899890133544109141796377101021618909140944172065627500517585 9549
UVM_INFO @ 2736740386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 104745902221013339602516872749553289602122982367535350648754516026060874400412 3712
UVM_INFO @ 558765192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 65952968101599694350795815747431141560193288786916695731370685926133031384333 2134
UVM_INFO @ 2717872453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 32233706700022577895420458711970217559747668767810061299260235013018151695482 8425
UVM_INFO @ 607511099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 38507132513236949071296435751268326652338283542626424536898781989199377593978 5479
UVM_INFO @ 717806763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 38689834848105817674088430764753755072888711866380218119391900482973125735953 1486
UVM_INFO @ 122322389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21947405801940524482010144755534760275674371364158660966916480463574552930860 2107
UVM_INFO @ 554176938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 84968940195796710047825319931193157119537779971636217718917049653161571881673 1704
UVM_INFO @ 298684408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 16959348982857069285569943051131524212821736883664932741583822438463544160083 6893
UVM_INFO @ 448902568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 834899812974718013931773390054606415298330853520020826315306967830243661513 2722
UVM_INFO @ 2025355699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 77022222908797801080730049842352032574308702535810580563396456814860017243133 772
UVM_INFO @ 1157189651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 64236280159908721745502876408914280785029647469807955870661767837676742389460 12377
UVM_INFO @ 15850557922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 43156046916822426405690852619218202963543300879224599633193026026958988283587 12373
UVM_INFO @ 220751660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 41198559935971480359576589951014641884630220708984389174959359797680750793577 568
UVM_INFO @ 104546842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 65748987428283523222195855711470560109562486052682041415171315176097704379336 1962
UVM_INFO @ 2216059786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 9856804951660677682909605125335117450436179422416600712403384782946110079677 16725
UVM_INFO @ 1272366937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 33610009254792708097828290918243767235603858144199841516783463392902480629531 2859
UVM_INFO @ 444374554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38212798031293044625187157795139369911023118506137200394485924232183964108316 6113
UVM_INFO @ 1341422525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 2222384855756226533300002598062648912177451763911471539221089431049195909800 3618
UVM_INFO @ 254601705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 24338325847672859148632751406185513873540156320149914484883493273954550884232 1570
UVM_INFO @ 2058724294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 34285378335702864741923003822026964548648380068378477496210966982352936166188 6347
UVM_INFO @ 1538111973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 113857908488410189934278427796711005220858108556524578804115080702519498674344 1605
UVM_INFO @ 126700315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 20489711004581833379632135180765713360102053980942577008667709648087626223253 7456
UVM_INFO @ 2576444759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 36970358790568905799773115055322631471878109505681338682849922103127551775971 5157
UVM_INFO @ 1353691658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 109512886254378701147357664152670023472409045309516985251895645123720839839010 3415
UVM_INFO @ 464768962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 14501846899125200997375590208752441290878531692170623613491098977827041757278 1937
UVM_INFO @ 939430510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 6861578350210425156945945344000583702074140896965923714920161599701803037971 1220
UVM_INFO @ 278551733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 91571047800301880133366329915782021982453317857776341404144580533773147406708 1877
UVM_INFO @ 2546475757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 53637553795849365627434445062783062464294531594303278410255049856725664462880 7922
UVM_INFO @ 2244836539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 18092749906534116960073233735715874787281192131035789481366854577319389934952 811
UVM_INFO @ 309257623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 35549085798147071294773426933235027639246243149246778962177250283170003906483 9486
UVM_INFO @ 659060282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 23291227997838409712333462370780889591721377931880521512457281332203692375827 22259
UVM_INFO @ 5261304366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 87134443289238127174982324121515028198043928033094720488311922015114385217580 11107
UVM_INFO @ 402874530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 66418488103886981157042394695993108404399700779342317778350563487636430027802 1900
UVM_INFO @ 652959589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 5476563131597350832922510468769752274616159456521479306451424496030450323691 5680
UVM_INFO @ 235861690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 114912458656769624635446397157739229699677392561209609269608901531433452726549 2245
UVM_INFO @ 1009474801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 27507204561702713441293357216629445895031436847584311204841016378313927943398 7199
UVM_INFO @ 542555409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 8400660384507387430389714596571769612108874449199333063286305414820871081722 9692
UVM_INFO @ 1715391597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 25595864903830741143814480620178356989762942108048377474567580183568842207053 611
UVM_INFO @ 131627451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 54106345679175942744891447280609360723855366575491526637669147878140120449880 2558
UVM_INFO @ 384002422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 96406570616547366525057844569991783095267596670440630114871778024883001520299 9273
UVM_INFO @ 605661872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 76461796896665637826781174446459720148245913583800030284576720458659160984088 2444
UVM_INFO @ 493965075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 42681232967976885054569746065396966537694913357254368957877180609590387824418 6304
UVM_INFO @ 441213084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 106820699609638623468872999592690245673642871593551526685620716229139494386264 1780
UVM_INFO @ 333503403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 43 test runs
otp_ctrl_init_fail 87059364969918297197319334896649712146062590204356043377780481677077160410240 3495
UVM_INFO @ 393799046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 86454720873295227986330959094060001245691404308458228060900282683313078649167 1857
UVM_INFO @ 2218946978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 59317766576905286158313950535100873169443468902152261263699257835374766527841 1775
UVM_INFO @ 2360694380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 58428629534918742894381768832736259653038767261448362527897206056468668288059 1623
UVM_INFO @ 2002800297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 68864049773309639933059256136977087996594387675144372992662894096704676215601 2583
UVM_INFO @ 1481883111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 49320159538086686547903697638365318579566521403093961136434432956728580555667 807
UVM_INFO @ 198516600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 51271401955127189531107016542265786160356145593959609329521954970337256244747 2261
UVM_INFO @ 1407062490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 98048900032940690332797234645340792116874323357910144603207907019232055263940 1637
UVM_INFO @ 2392039030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 72609886054448515338100429357193485033528274221766744918467596611554436308916 1503
UVM_INFO @ 461989067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 730311155343274808877127793047187478932688275578245441941548651009050903464 1585
UVM_INFO @ 1907650482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 114649922010228277585926198272921555193667623366928979091043219617321859169110 1649
UVM_INFO @ 307193527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 104626514124593970663878426966593860132229788640105739921933705418829705819400 1183
UVM_INFO @ 564108133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 52704502881476178023375493129891972202037517815946835211776005401081035246035 1313
UVM_INFO @ 458983375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 182352714790866145964994014856402054945745921285252484915736374367945403168 2289
UVM_INFO @ 1340372743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 106194055045173365675885609429510643292420920860812927164222561282179562659363 2275
UVM_INFO @ 1057027764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 56739094899147390820265966945052244434504653556967127048204126039062900476928 2371
UVM_INFO @ 402171164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 54326024256965362557907413591456011241563568722993006725935126816268325894522 2665
UVM_INFO @ 1187726444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 105680558393895295432069329423205471239256028959034493842453066086925465256531 1257
UVM_INFO @ 2070044829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 82026517671319418368289390254717150803798856688439583036099827510214100634863 3385
UVM_INFO @ 1408999399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 108531950606444856404062018517148690882258793557065214512294376925211362457927 2733
UVM_INFO @ 1391267952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 113479716451527040756427662659731550899236696655785545005665800998616335924881 2465
UVM_INFO @ 195804518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 88796788349835275038694065330671589384498996893262694543779284117690388565946 1769
UVM_INFO @ 527590029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 104794627550349951603059948204478612276785213888308409098215377107982071941989 1087
UVM_INFO @ 1856752985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 26868993384310437953729161734109841475432629122263106080848826801703557671567 1003
UVM_INFO @ 1805915705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 107382864919336694024644742821568604201063355271455857672265273478832317516299 1793
UVM_INFO @ 156934199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 68612919812204287112310635478765040112927075113673153712116183239433406916421 1447
UVM_INFO @ 1944417525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 59347881155367706399481589517339708330826922274192911649050525703018370360079 2745
UVM_INFO @ 118417836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 60701126149838222115540479839676644974954803599154098778503339544788132587394 1517
UVM_INFO @ 548324710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 35341523558867439456517991482472599061378819543356847927768176183992956319887 795
UVM_INFO @ 282987188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 76806501461727830014798327808963881216062681649500260602956305829607495951578 2291
UVM_INFO @ 1160549379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 103179716921840896761046639703170609356897899481917929874350741663239539087003 1563
UVM_INFO @ 577994025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 17590975358916188344817016572541242484207630788117366730124175180116502645900 1477
UVM_INFO @ 555582259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 58869762371287081802232917023459406984110611075797594810258338876503776565219 1703
UVM_INFO @ 1000673351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 71588411129535676775630956112588316655269686887291514847070611575128201481885 1485
UVM_INFO @ 292080715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 94707233663279965165459365658188298271122705040207206354733933389336083092936 1393
UVM_INFO @ 1936726350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 24879593921347007520335976912523222701011370959088733036236530161361758964267 2407
UVM_INFO @ 1114032516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 6120006989864583387654689295519524421318936475386853344884092723939596681624 1893
UVM_INFO @ 296572642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 8154815202160614047761400546984606856250786139233654664572743071675564900831 2387
UVM_INFO @ 206295941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 113082486622433147622793365326622445131052672299650868477198033159615746394679 1807
UVM_INFO @ 2504049986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 87350836799269951247707460596920521474927607492848136138535248597056633032768 1937
UVM_INFO @ 300142865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 98032784764155083745767017190715853715456002113310409728012704285993554982050 1017
UVM_INFO @ 506241413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 22006024458067051221357259178321555599030730929592155987219600566201500633394 1881
UVM_INFO @ 978920882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 43137600845188003269329314980957903895164029141170848752536084112553396875748 829
UVM_INFO @ 1279883618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 37 test runs
otp_ctrl_macro_errs 80903392554719312311011961842228890972414204825828707329222184937577707152789 1329
UVM_INFO @ 259957839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29580666666637482436368241805358295529147582933682275859200261644389800041390 2727
UVM_INFO @ 671142154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 108542719847785643812037320974355918538140605037303498464155620640496708916220 609
UVM_INFO @ 495018234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 1613591964637629313746863313146122009668174106834106067454103597548080178656 2183
UVM_INFO @ 1314992463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 10540336725324200148845084606748725789062388405041814636189662456948489324097 9420
UVM_INFO @ 8607980316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 67584262304159480065208230497772025448329149021834936380880370938974274460539 3652
UVM_INFO @ 431566672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 26928801789570307551727767118447083361636735210110763672248282291633899626358 6565
UVM_INFO @ 650855371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 10959715844133797457697937420452485719359173408826642647506011205535265926882 1336
UVM_INFO @ 489755141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71426807764076415957162050390377877596460749896541794073970700480060272235977 1129
UVM_INFO @ 15336655132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 40569076624216952806416119990776641338016082318642027497064301209556624715886 16334
UVM_INFO @ 1370934711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 71105892481105232717282779433957666781066480540519645145374236280990065342392 1874
UVM_INFO @ 1943439108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 73834400210836467846823597140237973626645163062404818446398281896196900758240 3180
UVM_INFO @ 1246211099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 6270956660493583295934055885416835090016093158730382273839150630813823146563 2271
UVM_INFO @ 3749106607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 65968913968462427613088960635588240990471963773488739508886304352217746159739 13605
UVM_INFO @ 868820949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81511370846529720720180874020483835853615088813423169288120024001605166309592 10228
UVM_INFO @ 2346928110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 86960702153376420401005743085119688036653158639097696870181311089627212983694 13364
UVM_INFO @ 4436565089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 80540462133518813036212206758393714094452398993223815805402291972310259290537 2964
UVM_INFO @ 486978703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 19437953205145490149471608439802279123177789992188805325663034300112917279398 693
UVM_INFO @ 76356755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 32869320103975660501307212055841631477132683281416508369063438274413954336980 3098
UVM_INFO @ 839623070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 99249444944048929654828389102765192135041152037390660223629613480786708480518 5334
UVM_INFO @ 3371442305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87200907958812595949963096578365966130695291490186803682170187381762152900557 2133
UVM_INFO @ 806105356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 88992398618735832754608471494425068815209716863438849664031863779392571504681 3583
UVM_INFO @ 824350825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 74234363936658256480887602963759245566527513581584061857470383319195670722711 3224
UVM_INFO @ 1231377473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 85672223127037201060379170793365199776714962395640704368738755957222238899051 459
UVM_INFO @ 254235859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85667268450208003671274836151830961102397301060203954286384229601112428832247 380
UVM_INFO @ 2294730056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 66848642346801339481475051912077116458541448174034495738882115238928349553263 7232
UVM_INFO @ 1220186497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26935683731896154993780630275957447306725023320049699517289700050624241229929 3572
UVM_INFO @ 1147196811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 47311476149712154370975883274120418947949434953057877303082904312943682123251 5981
UVM_INFO @ 1583798004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 95965026096974560189403055677965755372879732535406781693746344480709663300069 3534
UVM_INFO @ 354992398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 69835503077887498912884020634287493270017782101829915257350528734016573564761 3641
UVM_INFO @ 1514998265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91087055513815820074155668058579229182026474899681234688343415275220648405357 12632
UVM_INFO @ 4108435346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 59605229110419838927494220484102878223144612206745949829678587124301544137307 587
UVM_INFO @ 90338510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 34296899443989612688776852297830363900829954124635759262134792604098685787798 5063
UVM_INFO @ 201315191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64726342059735847327349002468642451542242154339574777056166630419498620828548 149
UVM_INFO @ 511210085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54235413201133897292410969119269722324039858067476294958246290805297049985906 4295
UVM_INFO @ 576049641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79541847893422417253896162912346405453989369263455714942096340629757009920692 215
UVM_INFO @ 39807381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104649234374850209520369880863689533595370082528431618014952982865751197731118 6418
UVM_INFO @ 28725180381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_check_error has unexpected timeout error 32 test runs
otp_ctrl_macro_errs 42264276622120944631517390236091918403131781446514614006450384035321738994526 849
UVM_INFO @ 231655508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 73486889566153414393007827605629326485542540274297152186220315159458727962389 1501
UVM_INFO @ 3001334919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 108791933594345053662800368585835445710618004195086390070294866051493039299220 3775
UVM_INFO @ 2814860827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 83393403698756099494783374958282040558185304826271704761342858452869884211244 300
UVM_INFO @ 864964260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 80643298638361537262927081459323400166110954589750183872430376211746427813860 1864
UVM_INFO @ 451003769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 66738657375847148463302296076251854652475641264408446118367342995936233388697 233
UVM_INFO @ 69917971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 49075474229911223505824906678326022396983184007456611331625494682212420004295 6758
UVM_INFO @ 2172777614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 87134823564261597540115199533533321378271692045620055924307044199498140827643 616
UVM_INFO @ 234704244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 21357257494048367090346913284532499447877904325466864137903503137990996891831 1133
UVM_INFO @ 2031169689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43529595719588706309585907560876570271003206077000004345732670872803653022492 4217
UVM_INFO @ 912313832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 82139571545405302790713104883249853050556328815605349326866141394539005791349 477
UVM_INFO @ 241738610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 29577011300493605135579809569350977096477558029462022985237438568181823997723 1283
UVM_INFO @ 101311171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 4944474561976533022243604506736911246386497622727828157928471282657311064222 4262
UVM_INFO @ 1511321412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39548099181188191203918447107455264695777232633026439775756237042781529153270 798
UVM_INFO @ 13686990596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 80460975056871201670603514433721042064046253701945893505960294729072560770460 2126
UVM_INFO @ 3817565935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 42231665840317618341564652526035518103444976095664404976531717173366547237229 5813
UVM_INFO @ 2108761838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102291005465097336845969389823744346589916770051781712597905562668369375631014 12258
UVM_INFO @ 51697222150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60517816519102765446778712287590723781145297937463227385998717228463494890801 2075
UVM_INFO @ 1300960785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 92254570799843294405401008998024821033419691982127235080334128304627974797500 4430
UVM_INFO @ 1278695095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 105468672173085384522334424555891544313672794203509495778150209805966973946785 3763
UVM_INFO @ 1718498341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 72541993776642685140551935400017004758511759391621082621651528225415061491874 1463
UVM_INFO @ 226517553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 54218948027177756534654013349868201359926862016083838862245929303863939145614 2894
UVM_INFO @ 418552412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 14646096708284747097451636330391547134121101168183595393953544733677795132295 2197
UVM_INFO @ 2507535938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 103902575409759290513019924045299849197888815797292908441023612911516604750353 2016
UVM_INFO @ 135156990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 47173985991651306474824895881711805828761602337610226563360188940029357993733 816
UVM_INFO @ 1099667438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 110614391054698058856110511626380702587038499833906898559969204922256348675374 4905
UVM_INFO @ 420449785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 59693000771411475838245479888861268835702046880052434650612782955732757649377 3956
UVM_INFO @ 1440268833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 43979299600567493595329931519886413235374572428127162115598515315263281047981 744
UVM_INFO @ 289164265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 2447363657435645714611198910439010833020481837727800073367046541961061765519 1374
UVM_INFO @ 1669757722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 24187495231359334612107993081862895606175791395060083283878706001282586206940 2830
UVM_INFO @ 295739358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 53216888666514830754768602941249223330268250615089885565871662428532291670748 989
UVM_INFO @ 1440253349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 108437535280572583804346028064680337456825702375261379205904177883441583103563 1051
UVM_INFO @ 1348545448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 17 test runs
otp_ctrl_stress_all_with_rand_reset 91901571521474096153489454143954906495355035403301268518634997570096998749928 1092
UVM_INFO @ 1199746872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111520047022421330889339825640140019790726043843954666105242235285292620813745 201
UVM_INFO @ 597789601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17552758184031906282495286353775914072443257832245777709890091085761371431263 32442
UVM_INFO @ 2407463601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7054273557962829446223775515557903025719438870053541448955504291003007617912 23986
UVM_INFO @ 13402418945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34439385257468552776993426160083127374528693401709459305775727278925424866306 5432
UVM_INFO @ 1624566103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72966328911620527088696521780438261821513160352521555745529221873019705458859 25511
UVM_INFO @ 4499337400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80272555661478552151937117074565696498112109234047194342483527703889756525004 11908
UVM_INFO @ 5638119274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37286517298045789547497497603375397895300774357295510865542433336179402627468 167
UVM_INFO @ 46578772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91818496620187904108744660210420934814035818814867878161361708219938980673217 177
UVM_INFO @ 36946094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61063577870107669067970451574500127607542971339436057536693742046158899181835 3150
UVM_INFO @ 3341091364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15098356316282511760540741717394604098699335708179904042679104917466011527306 4687
UVM_INFO @ 3818243012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 115040924314345126156328312545554656485544442843738523388123137508829752344290 1494
UVM_INFO @ 463492262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87705194123472206628165418346738254458350909016674961930287102511331505085735 141
UVM_INFO @ 534677075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6959713184088733083931266353826567030193074400023772463274053916568608325163 5237
UVM_INFO @ 3362088028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55743162099644415490383014615723270942299755757785006441788600516861984822022 1807
UVM_INFO @ 612905383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68092146765302972749365517311429256198023051316460452048134010686199466976714 295
UVM_INFO @ 2862776228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76770438843460021648493401593534242288996538808835887434929440239427337354415 215
UVM_INFO @ 74772540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_macro_error has unexpected timeout error 16 test runs
otp_ctrl_dai_errs 98358503262446524382081479048444361402204878531570368103935854725740458291826 1087
UVM_INFO @ 1478848579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 101157280225399786177362121900064494543584822166317320366611725618285173465104 3791
UVM_INFO @ 405723887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 64560459405623180657330035988022470736173740589516124403153028660693917432859 2015
UVM_INFO @ 624000286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 85106039984917793379648834983605538185660702267136809276063006795510021755132 19776
UVM_INFO @ 36769139210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 73474881767765089335894312387339063145850529263355453126219544347419480378863 5591
UVM_INFO @ 276195511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 28050263364940179552918390042811541760362003471370595330755775061953310760229 4695
UVM_INFO @ 291777298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 6107559164800900269797361671119072685924383415319699695374208509146400460997 3203
UVM_INFO @ 952836555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 36933026179593780475852679032633332754278343616696565339169193149405249666515 3560
UVM_INFO @ 886645829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 107014423433547055402810708219664418428424878865032858055595855813881806870878 952
UVM_INFO @ 1373351457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33696424041019188315678139586969136966764008251501131995648640398333494102501 3330
UVM_INFO @ 652504774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 88436134244790596909724408868761628782530920115278703058757933667624444383413 4987
UVM_INFO @ 377494716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 102450154815065195314203203126132933979860112339309914546992350331607949690019 5682
UVM_INFO @ 309721279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 16636311943151102840385331354912135382269195688285558207104140891485587131099 3144
UVM_INFO @ 857361371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 100779458439012768806472076597529040815726526025499082287248675129459170347923 11241
UVM_INFO @ 19515337756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 54852360589812723630314631432998581993298116427719147346667796043373395205260 5677
UVM_INFO @ 7190499260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44344943264316035275155659003128457596700789019192353766294063814328647679932 5404
UVM_INFO @ 17194359820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1824) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 14 test runs
otp_ctrl_stress_all_with_rand_reset 107186843695772764657391546922272599437403729957151805702849501765708861297053 99
UVM_INFO @ 429590223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15195835867926250729016041323019048232340386177415549027163807677167340435765 16224
UVM_INFO @ 8155724885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35509122279103689304169555670426708413023144222997495241610725460210745652145 1421
UVM_INFO @ 300777858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47930473971482593033207570967801556075068311234068186937735757849897410050439 2373
UVM_INFO @ 7722556174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113118507283661958983721218885673975949629404917372329851776686098023906766965 99
UVM_INFO @ 26786948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34859132863156208908717830310286655030487396583027502793273632602897578872536 99
UVM_INFO @ 29713059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16241337648700837266454166674419642400778309404220376600444365319576050217182 98
UVM_INFO @ 53595193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30084328420285717794178232083108669247088205490657570909478905301845613463609 30994
UVM_INFO @ 1972066793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102302582685716980937245174452870290848103358470597464407840392038343916329928 98
UVM_INFO @ 108001755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36027263582695106504259993196499199104886475658685080242211035759034977259792 14415
UVM_INFO @ 7487336663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75162436938371218787688492511262584957753618394738458777164789438798414406727 98
UVM_INFO @ 103521292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48853483241816262441402766211709410675585568971832944575023841638883071442488 3522
UVM_INFO @ 3571830417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21338395726270152297484941447508017038948558144549060495457582819539353967486 99
UVM_INFO @ 33301447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22741683955117271446348709796207388808804901185326429149070395153177956783699 98
UVM_INFO @ 430783078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 11 test runs
otp_ctrl_background_chks 565208732738264324190789409389684866847984468426220578115715002834584873925 15788
UVM_INFO @ 6703673491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 1084175903605355673083752385480690002650356599096220843284906240036225027117 5827
UVM_INFO @ 2385496446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25885795902476278837310774865077379380035177159956630538593644778703825915397 3403
UVM_INFO @ 1155987789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 90726703388352518842232919623814480951294673974948817914458709578444396110527 2763
UVM_INFO @ 12098345015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 30827213903586691744051909291906673031396754026965351526495980883970329947842 2400
UVM_INFO @ 2561918423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 58578435998426714357441095239413471363925097047768126183509223773460035992242 34107
UVM_INFO @ 1616006181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73636958326014078199718130186012759019196613799388992553666359990083063705393 1936
UVM_INFO @ 1119872221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97962181128843885427026474594824191113351058836351903497992074927595596571803 10302
UVM_INFO @ 2253163110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103981249387437676702158531959068291471503677101647598966473445227665728122599 4049
UVM_INFO @ 2513217447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58445441288004992116994980895598613469928843086277939029684629209343011830790 3626
UVM_INFO @ 8923329995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95843415881342413104272169672575399962045502080577876436614015080541555084747 47988
UVM_INFO @ 60928533781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_macro_error does not trigger! 11 test runs
otp_ctrl_init_fail 73198450777202985413868563294949842342149308922595728453009193176504961580967 1557
UVM_INFO @ 142089002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 2848432607354418723197095142169827964927540031819313709600102276209334061759 1249
UVM_INFO @ 201416240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 77847159123098359998763183190911255236143394293714519891375999731521515414431 1337
UVM_INFO @ 481175811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 45525741304802101404635050794116795020039086209082892698813079197134495565075 2417
UVM_INFO @ 1443963216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 88610495615729168424000477929628710774631515735138750430292534253913462716330 2451
UVM_INFO @ 209271571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 60581795198863808069610171734655342492413992369453754958602629388567342252236 1247
UVM_INFO @ 313467051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 69544437440486962098758763620104454119735113870779761494741920648530278482089 953
UVM_INFO @ 1684879640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 77893784902934496719433857193344993666241027809375732463857770167792484657097 1527
UVM_INFO @ 2100939469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 35547814649523201054986571954107371853520789335484516757848048823597364409720 2477
UVM_INFO @ 187259681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 60468843094883103145984325350624338459226440719018961130736592134279396929540 1487
UVM_INFO @ 337846175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 87461612331127592833634092759066072282739717090307301604284594695920803417310 1169
UVM_INFO @ 415335015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:786) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 10 test runs
otp_ctrl_stress_all_with_rand_reset 10968584002634512294255981149013904777764222454189720724972592276946818587245 98
UVM_INFO @ 52852133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50243327012219907391151008235369444204658493709656380899751871207106995607345 98
UVM_INFO @ 26915239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18849504485760832124431018183235672770001949919809559389444586643587620607225 98
UVM_INFO @ 103904074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105804435011908206509616677092849532405022068123114953192064439948109791943546 98
UVM_INFO @ 111955920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97327025729877317911043893260651508133223321647500690444606520682328991116496 98
UVM_INFO @ 78587055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8293356875866374684381040277370079207129665214758129723428943838609463378958 775
UVM_INFO @ 394144492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41933681263426596289182226907772393711251820806681915811358056270613483432937 4867
UVM_INFO @ 2060821555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73279204164355731985462998431719693371623248934972967534566459447906518050188 49663
UVM_INFO @ 4965805840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106230539489756561283491864071193754031459635717617533282140475625203933534296 1432
UVM_INFO @ 226275358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25809803740689426894678603879732501702702050019114081035195921445405536681106 17948
UVM_INFO @ 1192012946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles 7 test runs
otp_ctrl_stress_all 50818582971068081899063551379301108195993767745908393917268673065359766962365 39879
UVM_INFO @ 27868421698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 35702702756501459614115346458842955933437486236172962691981573806725938196030 3271
UVM_INFO @ 300506658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 6111919252046763277525846813279775477811584257076518480852895048357562955477 5081
UVM_INFO @ 768632383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 3941196582980992209067767508074998275857961802633888120828918833720055096328 9481
UVM_INFO @ 559687754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109394332505675871258450079731063204602643877599976146273335401543968619412176 3139
UVM_INFO @ 1488580135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25755395863956245494163905935719586822728309825579014690617266869940317090616 2255
UVM_INFO @ 948973405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56763605280685484700192534562233904987877051998085832466073120485846900965908 30320
UVM_INFO @ 3786632574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_prim_otp_alert) did not fire in * cycles. 5 test runs
otp_ctrl_tl_intg_err 106094171673661109235858165024620050404439333481361233008718566247520493422961 216
UVM_INFO @ 7909926538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_tl_intg_err 30717106516196918509178142021608133189687223030510856582179359975083935967079 145
UVM_INFO @ 2941689744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_tl_intg_err 94998028809206510936901768530231540050552338220382809402658383607504262448439 108
UVM_INFO @ 955341920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_tl_intg_err 25244384697664929984733284046029387458487339436985529450395357678834740718526 275
UVM_INFO @ 2042905653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_tl_intg_err 95282680065945708993645530231309020704881319151686673091897901780777987131844 417
UVM_INFO @ 17985880264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_bus_integ_error) did not fire in * cycles. 3 test runs
otp_ctrl_tl_intg_err 77030698045771588276075326131710480287444455855992914197253930928971663306453 235
UVM_INFO @ 8422448396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_tl_intg_err 109256029420091717011119686163097318571653234043425716698414020107659628878688 315
UVM_INFO @ 13472237543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_tl_intg_err 38582085889152491990698004870944674304026768586759762353692726569438484275386 152
UVM_INFO @ 273695920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_stress_all_with_rand_reset 46642650086610929663122393885768528345038424707077245535966341247340743674635 3939
UVM_INFO @ 10145866026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_check_error) did not fire in * cycles. 1 test run
otp_ctrl_sec_cm 23018683170464489361136885894866168331644774380128836349384094581957211893703 135
UVM_INFO @ 2748995659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_macro_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
otp_ctrl_dai_errs 96528171503497727159720459669834999368133879424574176100186924840605116540040 5630
UVM_INFO @ 1569820653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
otp_ctrl_stress_all_with_rand_reset 21485078875661289833502987445005008513974524626591226053497854220071519382426 None
Offending '(cio_test_en_o == *)' 1 test run
otp_ctrl_stress_all_with_rand_reset 102487677695991739969995576019314857496545433927945961871249456691459328071590 7842
UVM_ERROR @ 1433686712 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 1433686712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---