Simulation Results: rom_ctrl/192kb

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.38 %
  • code
  • 98.63 %
  • assert
  • 97.24 %
  • func
  • 99.28 %
  • line
  • 99.21 %
  • branch
  • 99.64 %
  • cond
  • 98.96 %
  • toggle
  • 95.34 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 36.850s 7663.588us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 34.610s 103.478us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 17.690s 63.924us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 23.590s 123.179us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 17.770s 57.314us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 18.710s 98.147us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 17.690s 63.924us 5 5 100.00
rom_ctrl_csr_aliasing 17.770s 57.314us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 16.050s 111.879us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 17.280s 93.029us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 28.930s 2143.503us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 115.800s 3149.146us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 53.080s 2069.496us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 19.130s 99.350us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 35.970s 1065.610us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 35.970s 1065.610us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 34.610s 103.478us 1 1 100.00
rom_ctrl_csr_rw 17.690s 63.924us 5 5 100.00
rom_ctrl_csr_aliasing 17.770s 57.314us 1 1 100.00
rom_ctrl_same_csr_outstanding 34.720s 77.058us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 34.610s 103.478us 1 1 100.00
rom_ctrl_csr_rw 17.690s 63.924us 5 5 100.00
rom_ctrl_csr_aliasing 17.770s 57.314us 1 1 100.00
rom_ctrl_same_csr_outstanding 34.720s 77.058us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 805.580s 37409.179us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 114.380s 16475.138us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 2955.110s 453.010us 5 5 100.00
rom_ctrl_tl_intg_err 646.800s 318.119us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 2955.110s 453.010us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 2955.110s 453.010us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 805.580s 37409.179us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 805.580s 37409.179us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 805.580s 37409.179us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 805.580s 37409.179us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 805.580s 37409.179us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 2955.110s 453.010us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 2955.110s 453.010us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 36.850s 7663.588us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 36.850s 7663.588us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 36.850s 7663.588us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 646.800s 318.119us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 805.580s 37409.179us 20 20 100.00
rom_ctrl_kmac_err_chk 53.080s 2069.496us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 805.580s 37409.179us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 805.580s 37409.179us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 805.580s 37409.179us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 114.380s 16475.138us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 2955.110s 453.010us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
rom_ctrl_stress_all_with_rand_reset 360.440s 55567.518us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 48177589235484862592858922342348298443857408947365695992280368220841392488989 85
UVM_INFO @ 2143502710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 48939819704319731500741116354100385419206142372741634757135667849496061818611 85
UVM_INFO @ 5666504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 2 test runs
rom_ctrl_stress_all_with_rand_reset 93093263686175253563532208740788873937301023294436329122563767613838436084261 87
UVM_INFO @ 4171859151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 41931421549527010963800762736131249911558937945895147421029590100290807051570 88
UVM_INFO @ 2535775114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---