Simulation Results: rstmgr

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.12 %
  • code
  • 99.66 %
  • assert
  • 98.93 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.31 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 2.230s 285.625us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.370s 147.661us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.230s 71.828us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 8.700s 1441.674us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.380s 111.274us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.900s 122.857us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.230s 71.828us 5 5 100.00
rstmgr_csr_aliasing 1.380s 111.274us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 1.370s 182.451us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 2.970s 479.293us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.780s 183.696us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 10.430s 2536.977us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 10.430s 2536.977us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 10.430s 2536.977us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 10.430s 2536.977us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 67.480s 13548.190us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.210s 77.662us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 4.190s 531.878us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 4.190s 531.878us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.370s 147.661us 1 1 100.00
rstmgr_csr_rw 1.230s 71.828us 5 5 100.00
rstmgr_csr_aliasing 1.380s 111.274us 1 1 100.00
rstmgr_same_csr_outstanding 1.680s 137.625us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.370s 147.661us 1 1 100.00
rstmgr_csr_rw 1.230s 71.828us 5 5 100.00
rstmgr_csr_aliasing 1.380s 111.274us 1 1 100.00
rstmgr_same_csr_outstanding 1.680s 137.625us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
rstmgr_sec_cm 42.160s 18045.556us 5 5 100.00
rstmgr_tl_intg_err 4.500s 963.960us 24 25 96.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 42.160s 18045.556us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 42.160s 18045.556us 5 5 100.00
sec_cm_bus_integrity 24 25 96.00
rstmgr_tl_intg_err 4.500s 963.960us 24 25 96.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.670s 205.155us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 25 25 100.00
rstmgr_leaf_rst_cnsty 12.970s 2558.960us 25 25 100.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 1.790s 301.735us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 42.160s 18045.556us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.230s 71.828us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.230s 71.828us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [rstmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
rstmgr_tl_intg_err 869590257680784387634971933395117553699739759565775588201104522854366118333 152
UVM_INFO @ 403977760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---