Simulation Results: rstmgr_cnsty_chk

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.81 %
  • code
  • 95.61 %
  • assert
  • 100.00 %
  • line
  • 98.46 %
  • branch
  • 98.39 %
  • cond
  • 88.89 %
  • toggle
  • 100.00 %
  • FSM
  • 92.31 %
Validation stages
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
rstmgr_cnsty_chk_test 4.870s 11070.276us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) 1 test run
rstmgr_cnsty_chk_test 38939450068291098107111973283326851680743911323680976749883300069843974957189 175
UVM_INFO @ 2056764970 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 2077244970 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 2097724970 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 2118204970 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16