Simulation Results: rv_timer

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.60 %
  • code
  • 94.66 %
  • assert
  • 98.73 %
  • func
  • 99.41 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
55.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.960s 1291.961us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.850s 44.252us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 0.870s 51.722us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 4.010s 2057.508us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.770s 17.973us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.590s 213.093us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 0.870s 51.722us 5 5 100.00
rv_timer_csr_aliasing 0.770s 17.973us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 20 20 100.00
rv_timer_random_reset 30.460s 102704.403us 20 20 100.00
disabled 20 20 100.00
rv_timer_disabled 8.670s 4060.404us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 587.560s 302915.795us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 587.560s 302915.795us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 10.190s 4707.342us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 0.860s 28.719us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 0.870s 72.499us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.020s 178.048us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.020s 178.048us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 0.850s 44.252us 1 1 100.00
rv_timer_csr_rw 0.870s 51.722us 5 5 100.00
rv_timer_csr_aliasing 0.770s 17.973us 1 1 100.00
rv_timer_same_csr_outstanding 1.170s 37.615us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 0.850s 44.252us 1 1 100.00
rv_timer_csr_rw 0.870s 51.722us 5 5 100.00
rv_timer_csr_aliasing 0.770s 17.973us 1 1 100.00
rv_timer_same_csr_outstanding 1.170s 37.615us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.210s 104.019us 5 5 100.00
rv_timer_tl_intg_err 1.750s 132.369us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 1.750s 132.369us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 10 10.00
rv_timer_min 2.280s 855.567us 1 10 10.00
max_value 1 10 10.00
rv_timer_max 1.350s 1000.651us 1 10 10.00
stress_all_with_rand_reset 20 20 100.00
rv_timer_stress_all_with_rand_reset 51.570s 27914.594us 20 20 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 9 test runs
rv_timer_min 2139339606117382778681800965179306934416297513706255985435431169474859738023 81
UVM_INFO @ 79181495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 6754677244950574991917686340008372263212258074577512609282721959995761532115 82
UVM_INFO @ 855567264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 19681140138908723890600209144534502235409411320597512001700559333818221645253 81
UVM_INFO @ 62567113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 107553023872457906007897794510953446159300387020629528647389095446204753446987 81
UVM_INFO @ 239781314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 95060506213644950792700124087461550978874208835245544794413262089552111013074 83
UVM_INFO @ 63475910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 41196449387304097535204313802267184807393379126770719637543940844292239428490 81
UVM_INFO @ 443014427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 42449698947896633245434572451495447237923358083361389067333075496619463133024 82
UVM_INFO @ 298653470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 26334970216010730045282734676300475024947902905640063620559435013042560209195 81
UVM_INFO @ 65792222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 25829740819061771599985036814402817111709049028977139591681126568803186602759 82
UVM_INFO @ 82934686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 8 test runs
rv_timer_max 21028963940205181303886640981303249109258792364749737242991974135654379430532 81
UVM_INFO @ 92456562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 62202446341929786400606657707830151142037670238915172532968043503052780176491 82
UVM_INFO @ 1000651314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 6076394931975854709906678480314703919210695222530622629417741110323866229164 81
UVM_INFO @ 90455476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 43310380972556536174064539992950046463763999856257716866098845854550434273660 81
UVM_INFO @ 45663381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 22429375382190518545742464108138167758430489321187378010577255317019694583062 81
UVM_INFO @ 44967970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 95556837027733025011164173522568887630042577732824484209050463471084004217173 81
UVM_INFO @ 171624374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 70287154270273460583061826539836097140083221233277941655299618091816969104762 81
UVM_INFO @ 46973718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 98146535917714636299971189524167815698371895514931228451908251414708172516172 81
UVM_INFO @ 128902264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:342) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 111767270771043590067169503068460416757573318491185249443107524964479683084398 81
UVM_INFO @ 88066710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---