| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
80.68% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 1431.808us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 51.561us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 37.936us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 2.000s | 250.959us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 2.000s | 37.468us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 6.000s | 1471.102us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 37.936us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 37.468us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 338.000s | 23192.129us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 183.000s | 62187.325us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 52.000s | 25961.336us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 295.000s | 36325.661us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 275.000s | 79621.132us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 107.000s | 15277.483us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 88.000s | 72430.982us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 44.000s | 11599.344us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 8.000s | 692.646us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 458.000s | 24791.623us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 10.000s | 9531.769us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 33.000s | 2892.928us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 9.000s | 2683.441us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 18.000s | 10638.181us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 4.000s | 513.715us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 1431.808us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 8.000s | 692.646us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 107.000s | 15277.483us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 567.000s | 294108.098us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 24.740us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 692.361us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 692.361us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 51.561us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 37.936us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 37.468us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 20.160us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 51.561us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 37.936us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 37.468us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 20.160us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 4 | 5 | 80.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 45.000s | 39185.922us | 4 | 5 | 80.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1391.403us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 975.309us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1391.403us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 975.309us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 18.000s | 10638.181us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 18.000s | 10638.181us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 37.936us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 44.000s | 11599.344us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 44.000s | 11599.344us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 44.000s | 11599.344us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 88.000s | 72430.982us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3602.126s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 4 | 5 | 80.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 45.000s | 39185.922us | 4 | 5 | 80.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 1431.808us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 1431.808us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 44.000s | 11599.344us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1391.403us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 88.000s | 72430.982us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1391.403us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1391.403us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 1431.808us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1391.403us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 52.000s | 2141.472us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 52730639340438337429936582459476205523888677254965063620385084518544420282166 | None | ||
| sram_ctrl_mubi_enc_err | 70517496625593637348014843230258508171882800764341615144815050185954405868893 | None | ||
| sram_ctrl_readback_err | 28513058583819817685645247708100623920981203724085186367764687909677600958973 | None | ||
| sram_ctrl_mubi_enc_err | 16162516967711948792659269960025070614270810682253145736135503913867406682510 | None | ||
| sram_ctrl_readback_err | 86639091517145100361967144726567425954313134392490074725518644087499953621514 | None | ||
| sram_ctrl_mubi_enc_err | 88812607415381182665598662526405299518493145298940120254572595919683335070703 | None | ||
| sram_ctrl_readback_err | 76831474036270725522558464796434133625942041071923871057258480623811784052297 | None | ||
| sram_ctrl_mubi_enc_err | 1508907448287081920374112428124267547434371147696605600522637349534423441440 | None | ||
| sram_ctrl_readback_err | 60875491441497104823072889257322186731984764922409883270950792513210938220601 | None | ||
| sram_ctrl_mubi_enc_err | 40441267314114181583980015953709364790120756497080008478865909616283598060945 | None | ||
| sram_ctrl_readback_err | 3504913971026185354149668807022159524700913435335641221668336618569503300183 | None | ||
| sram_ctrl_mubi_enc_err | 86790026851947119202709399943821255083028937840321700394263216594308165207276 | None | ||
| sram_ctrl_readback_err | 5845907832343311896420177936725146700952709819444904217494210951829747444881 | None | ||
| sram_ctrl_mubi_enc_err | 74700132473587159804183507856970055696673412022622234504111213952671994252794 | None | ||
| sram_ctrl_readback_err | 46297163852436971750219662490654086163446793802985306640634192145778745940710 | None | ||
| sram_ctrl_mubi_enc_err | 105974432205810585111303878349563223203074302073363969374934830286843424164640 | None | ||
| UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_error has unexpected timeout error | 1 test run | |||
| sram_ctrl_passthru_mem_tl_intg_err | 30066405858402972542692492140642121516299876288201047769828326380751221622193 | 143 |
UVM_INFO @ 25431415571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|