| V1 |
|
94.59% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 50.593us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 31.410us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 20.590us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 2.000s | 204.805us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 2.000s | 19.160us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 3 | 5 | 60.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 3.000s | 43.678us | 3 | 5 | 60.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 20.590us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 19.160us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 13.000s | 2706.346us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 6.000s | 749.520us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 15.000s | 557.380us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 273.000s | 4308.018us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 13.000s | 7941.783us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 26.000s | 789.020us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 4023.653us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 17.000s | 8126.428us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 2.000s | 191.232us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 475.000s | 111252.196us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 3.000s | 36.319us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 3.000s | 143.675us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 3.000s | 135.455us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 17.000s | 3446.798us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 45.689us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 50.593us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 2.000s | 191.232us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 26.000s | 789.020us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 74.000s | 9231.634us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 13.842us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 130.500us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 130.500us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 31.410us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 20.590us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 19.160us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 128.714us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 31.410us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 20.590us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 19.160us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 128.714us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 3279.003us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1940.056us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 874.621us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1940.056us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 874.621us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 17.000s | 3446.798us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 17.000s | 3446.798us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 20.590us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 17.000s | 8126.428us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 17.000s | 8126.428us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 17.000s | 8126.428us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 4023.653us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3600.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 3279.003us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3600.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 50.593us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 50.593us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 17.000s | 8126.428us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1940.056us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 4023.653us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1940.056us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1940.056us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 50.593us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1940.056us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 73.000s | 1555.076us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 25894590376402212956800244698048445416294298365946432398118557498712901513711 | None | ||
| sram_ctrl_mubi_enc_err | 89961836630349679108808220877126208823932893897812745361471972590611482799921 | None | ||
| sram_ctrl_readback_err | 96017885967172418449593894689151483043636980990401498354503586951052495857559 | None | ||
| sram_ctrl_mubi_enc_err | 98127005296117519465004731119212418735930926998463517390285831570287040472450 | None | ||
| sram_ctrl_readback_err | 50709662001104965199439795954396700840785868253302472047262829171700009231357 | None | ||
| sram_ctrl_mubi_enc_err | 96020057980823412090211071376044875180924879070421390454472226775858507005694 | None | ||
| sram_ctrl_readback_err | 105172909517972589195368360180735800061545999790471953496029686897733512703593 | None | ||
| sram_ctrl_mubi_enc_err | 73340528304326237753903923202398027062612785636682050153747812349048440726737 | None | ||
| sram_ctrl_readback_err | 17846431958200155556667990318711485875471653678217308922792542343033776266609 | None | ||
| sram_ctrl_mubi_enc_err | 40164051007290476790309963827666434175815294926652573833313804493968744019315 | None | ||
| sram_ctrl_readback_err | 112637615452121711962238372024701902329451841422701457322741341841028179400433 | None | ||
| sram_ctrl_mubi_enc_err | 25299921256597193911891917132671348440841276497490136377853810433373023090225 | None | ||
| sram_ctrl_readback_err | 89486095116494938838766932453499931052958398335194070138285958692769878517980 | None | ||
| sram_ctrl_mubi_enc_err | 86180189567022688517643678579988487504584259362395911812415706397852776221245 | None | ||
| sram_ctrl_readback_err | 9805048296956253257567232436248079132002080017349179953379589591674098710054 | None | ||
| sram_ctrl_mubi_enc_err | 101937460878946877175092807712347801244490632362815665165279397436149193659032 | None | ||
| UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) | 2 test runs | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 42315409001208651405535337053660029174884072080953096053275459569596845451182 | 98 |
UVM_INFO @ 43580954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sram_ctrl_csr_mem_rw_with_rand_reset | 114532292181776862745662289435583622694361822132325322629884111882946375831233 | 98 |
UVM_INFO @ 52670498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|