Simulation Results: uart

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.83 %
  • code
  • 92.64 %
  • assert
  • 98.56 %
  • func
  • 99.30 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.25 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
96.98%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 18.640s 6165.594us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.890s 56.013us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 0.930s 24.557us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.770s 138.586us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.960s 44.591us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 1.160s 37.293us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 0.930s 24.557us 5 5 100.00
uart_csr_aliasing 0.960s 44.591us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 255.170s 199828.050us 10 10 100.00
parity 20 20 100.00
uart_smoke 18.640s 6165.594us 10 10 100.00
uart_tx_rx 255.170s 199828.050us 10 10 100.00
parity_error 20 20 100.00
uart_intr 150.080s 339970.551us 10 10 100.00
uart_rx_parity_err 422.950s 159986.760us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 255.170s 199828.050us 10 10 100.00
uart_intr 150.080s 339970.551us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 263.990s 149936.610us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 288.650s 115686.575us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 500.130s 303692.296us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 150.080s 339970.551us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 150.080s 339970.551us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 150.080s 339970.551us 10 10 100.00
perf 10 10 100.00
uart_perf 686.920s 20372.403us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 19.700s 9171.317us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 19.700s 9171.317us 10 10 100.00
rx_noise_filter 1 10 10.00
uart_noise_filter 24.980s 54296.073us 1 10 10.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 47.730s 36588.964us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 19.120s 6968.239us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 45.260s 6141.265us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 1311.990s 139946.136us 10 10 100.00
stress_all 7 10 70.00
uart_stress_all 762.240s 586364.319us 7 10 70.00
alert_test 10 10 100.00
uart_alert_test 0.900s 50.637us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 0.930s 31.676us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 2.770s 145.774us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 2.770s 145.774us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 0.890s 56.013us 1 1 100.00
uart_csr_rw 0.930s 24.557us 5 5 100.00
uart_csr_aliasing 0.960s 44.591us 1 1 100.00
uart_same_csr_outstanding 1.090s 18.750us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 0.890s 56.013us 1 1 100.00
uart_csr_rw 0.930s 24.557us 5 5 100.00
uart_csr_aliasing 0.960s 44.591us 1 1 100.00
uart_same_csr_outstanding 1.090s 18.750us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 1.410s 196.578us 5 5 100.00
uart_tl_intg_err 1.750s 1339.157us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 1.750s 1339.157us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
uart_stress_all_with_rand_reset 58.530s 4016.242us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 10 test runs
uart_noise_filter 4539479955348126140987447267731647954284304128411688741080568075147982147724 81
UVM_ERROR @ 2450155797 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 3596081631 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60 [0x3c] vs 199 [0xc7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 5717848605 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5717848605 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
uart_noise_filter 70119493600712605978466426347840241959138200172759235771900095253882208014284 83
UVM_ERROR @ 7996990992 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 7998430992 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 7998430992 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8002370992 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
uart_noise_filter 34814058721025545830026152155387376303910924938195363250853982533925387475178 81
UVM_ERROR @ 3877774109 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3877835963 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3883907964 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3890062437 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 101533286058014681782135518451638083697565477380060969151054529244448332806516 89
UVM_ERROR @ 16972601270 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 19403443760 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 19403443760 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 19403443760 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
uart_noise_filter 105871846624745516976813335587056376831975037882392544842776841945801154188217 85
UVM_ERROR @ 26165675493 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 26165955493 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 26166175493 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 26167055493 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 23207159677257503841140973799687880536813561409096810929692439781091787393863 80
UVM_ERROR @ 1435909638 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 2583829638 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 3208109638 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 3208109638 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 104959144604674561882371174549003017550835483018168876064169183481927675109196 80
UVM_ERROR @ 77448016 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 78468016 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 79568016 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 80658016 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 50984354974177428955188671140342673083313552473244577967580571099808824930057 83
UVM_ERROR @ 50857253698 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 51221506612 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 51336340864 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 51336340864 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 44074308395766463430864839204750993876180420939915654162519588983099049903053 112
UVM_ERROR @ 461344918032 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 461344918032 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 462491635539 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 462492427212 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 21735337373613288870548716722918414267889211520980859356183277816022709329548 146
UVM_ERROR @ 6627061097 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6630144455 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6632644475 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_INFO @ 6759103820 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/254
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 2 test runs
uart_stress_all 112718849680609413049130211458959409188868451137222319944615177215241306876733 99
UVM_ERROR @ 20617764960 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 20617775164 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (25 [0x19] vs 215 [0xd7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 20617805776 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 20617826184 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_stress_all_with_rand_reset 102595126362854665925251970079541770241484091148043964152931880882048380656807 96
UVM_ERROR @ 1984388860 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1984769812 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1984865050 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1985055526 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 231 [0xe7]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 3233497743033724487512156725641818951989102209049392105588514288736595557127 80
UVM_ERROR @ 386365904 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 386365904 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 450088636 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 450088636 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr 1 test run
uart_noise_filter 92980744909857915450309004899572551965016979824057696744160558726289121767967 80
UVM_ERROR @ 90406645 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 90406645 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
UVM_ERROR @ 90937912 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 90937912 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark