Simulation Results: adc_ctrl

 
12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.57 %
  • code
  • 98.53 %
  • assert
  • 96.92 %
  • func
  • 19.26 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 95.08 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
93.22%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
adc_ctrl_smoke 16.020s 5864.379us 10 10 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.340s 700.424us 1 1 100.00
csr_rw 5 5 100.00
adc_ctrl_csr_rw 1.570s 423.469us 5 5 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 11.630s 33357.895us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.550s 500.173us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.460s 483.631us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
adc_ctrl_csr_rw 1.570s 423.469us 5 5 100.00
adc_ctrl_csr_aliasing 1.550s 500.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 10 10 100.00
adc_ctrl_filters_polled 162.740s 55142.217us 10 10 100.00
filters_polled_fixed 10 10 100.00
adc_ctrl_filters_polled_fixed 98.500s 35645.687us 10 10 100.00
filters_interrupt 10 10 100.00
adc_ctrl_filters_interrupt 140.050s 50923.587us 10 10 100.00
filters_interrupt_fixed 10 10 100.00
adc_ctrl_filters_interrupt_fixed 104.880s 36091.237us 10 10 100.00
filters_wakeup 10 10 100.00
adc_ctrl_filters_wakeup 157.440s 51411.307us 10 10 100.00
filters_wakeup_fixed 10 10 100.00
adc_ctrl_filters_wakeup_fixed 225.270s 72874.888us 10 10 100.00
filters_both 10 10 100.00
adc_ctrl_filters_both 194.700s 67116.139us 10 10 100.00
clock_gating 0 10 0.00
adc_ctrl_clock_gating 15.030s 24428.139us 0 10 0.00
poweron_counter 10 10 100.00
adc_ctrl_poweron_counter 16.050s 5188.100us 10 10 100.00
lowpower_counter 10 10 100.00
adc_ctrl_lowpower_counter 98.210s 36326.736us 10 10 100.00
fsm_reset 10 10 100.00
adc_ctrl_fsm_reset 266.850s 112828.098us 10 10 100.00
stress_all 8 10 80.00
adc_ctrl_stress_all 424.480s 204254.259us 8 10 80.00
alert_test 10 10 100.00
adc_ctrl_alert_test 1.870s 388.657us 10 10 100.00
intr_test 10 10 100.00
adc_ctrl_intr_test 2.390s 448.906us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
adc_ctrl_tl_errors 4.580s 546.585us 25 25 100.00
tl_d_illegal_access 25 25 100.00
adc_ctrl_tl_errors 4.580s 546.585us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
adc_ctrl_csr_hw_reset 1.340s 700.424us 1 1 100.00
adc_ctrl_csr_rw 1.570s 423.469us 5 5 100.00
adc_ctrl_csr_aliasing 1.550s 500.173us 1 1 100.00
adc_ctrl_same_csr_outstanding 16.680s 5513.974us 5 5 100.00
tl_d_partial_access 12 12 100.00
adc_ctrl_csr_hw_reset 1.340s 700.424us 1 1 100.00
adc_ctrl_csr_rw 1.570s 423.469us 5 5 100.00
adc_ctrl_csr_aliasing 1.550s 500.173us 1 1 100.00
adc_ctrl_same_csr_outstanding 16.680s 5513.974us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
adc_ctrl_sec_cm 11.250s 8306.328us 5 5 100.00
adc_ctrl_tl_intg_err 26.310s 8002.765us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
adc_ctrl_tl_intg_err 26.310s 8002.765us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
adc_ctrl_stress_all_with_rand_reset 16.480s 11107.087us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 13 test runs
adc_ctrl_clock_gating 66461990375010596323565333192274470622289032539555371137071506676572541034779 392
UVM_INFO @ 9341413193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 2378337884389712263515098817492405805554606946133461845224796246696466506745 429
UVM_INFO @ 3742086095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 71680906699895438337187093771961016756529245901520038903645779799745660776731 392
UVM_INFO @ 6596779800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 15868398497040617335758547468280540326750529480864435247650604562643766704228 399
UVM_INFO @ 24428139481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 47556342761614478262702325448443019221488372806325978362392947551193581053895 392
UVM_INFO @ 1651463771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 74040830397500450168843601434969707314843213779224461397695416158290751987040 392
UVM_INFO @ 1081780454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 20438146215498659727753652684619090399646283640695501271969828872484293282315 402
UVM_INFO @ 28995601729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 29578464792712867894595288870181677047785714003269825288013734752887432017221 392
UVM_INFO @ 2677443094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 10326624481871234594566489955090431834049689683608672900998196617361847765941 416
UVM_INFO @ 42405319797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 74523890259500243316105104308461148857503918130103880875194103122212291621364 392
UVM_INFO @ 1794285017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 17007661700655566001992035427057197177871937577074978324451765404911125998282 392
UVM_INFO @ 1622838010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 42389915857169297207625168580881916297061182552798393593183933959812552102193 400
UVM_INFO @ 22661086336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 112943569799182343246236548408536394186409652784352625423944055591998936984366 399
UVM_INFO @ 23329386844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---