Simulation Results: chip

 
12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.12 %
  • code
  • 77.31 %
  • assert
  • 97.22 %
  • func
  • 98.83 %
  • line
  • 94.04 %
  • branch
  • 94.47 %
  • cond
  • 92.66 %
  • toggle
  • 72.04 %
  • FSM
  • 33.33 %
Validation stages
V1
99.20%
V2
87.23%
V2S
83.33%
V3
82.05%
unmapped
13.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 9 9 100.00
chip_sw_example_rom 171.160s 2032.288us 3 3 100.00
chip_sw_example_manufacturer 327.990s 2287.186us 3 3 100.00
chip_sw_example_concurrency 418.260s 2772.760us 3 3 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 1058.550s 12841.534us 1 1 100.00
csr_rw 5 5 100.00
chip_csr_rw 1216.910s 12562.867us 5 5 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 5002.630s 35848.917us 1 1 100.00
csr_aliasing 0 1 0.00
chip_csr_aliasing 10800.199s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 5 5 100.00
chip_csr_mem_rw_with_rand_reset 1595.420s 18057.089us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 5 6 83.33
chip_csr_aliasing 10800.199s 0.000us 0 1 0.00
chip_csr_rw 1216.910s 12562.867us 5 5 100.00
xbar_smoke 50 50 100.00
xbar_smoke 12.360s 222.577us 50 50 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 666.400s 4017.617us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 666.400s 4017.617us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 666.400s 4017.617us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 780.320s 3876.270us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 780.320s 3876.270us 5 5 100.00
chip_sw_uart_tx_rx_idx1 835.470s 4234.855us 5 5 100.00
chip_sw_uart_tx_rx_idx2 787.830s 4414.832us 5 5 100.00
chip_sw_uart_tx_rx_idx3 820.950s 4422.964us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 3408.020s 13560.949us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 3300.260s 12967.593us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1301.140s 8599.500us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 9 10 90.00
chip_padctrl_attributes 928.870s 11651.421us 9 10 90.00
chip_padctrl_attributes 9 10 90.00
chip_padctrl_attributes 928.870s 11651.421us 9 10 90.00
chip_sw_sleep_pin_mio_dio_val 3 3 100.00
chip_sw_sleep_pin_mio_dio_val 441.850s 3273.214us 3 3 100.00
chip_sw_sleep_pin_wake 1 3 33.33
chip_sw_sleep_pin_wake 618.810s 5978.294us 1 3 33.33
chip_sw_sleep_pin_retention 0 3 0.00
chip_sw_sleep_pin_retention 409.010s 3315.389us 0 3 0.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1710.970s 12949.666us 5 5 100.00
chip_tap_straps_testunlock0 1072.780s 9916.256us 5 5 100.00
chip_tap_straps_rma 1339.880s 9723.896us 5 5 100.00
chip_tap_straps_prod 2281.840s 17061.261us 5 5 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 951.380s 5073.364us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 951.380s 5073.364us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 1253.510s 7719.756us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 2498.170s 13336.396us 0 3 0.00
chip_sw_ast_sys_clk_jitter 24 24 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6170.960s 18764.503us 3 3 100.00
chip_sw_aes_enc_jitter_en 398.760s 2768.385us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1460.240s 6887.658us 3 3 100.00
chip_sw_hmac_enc_jitter_en 409.440s 3261.901us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 2848.950s 11943.245us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 440.900s 3133.962us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 815.950s 4680.027us 3 3 100.00
chip_sw_clkmgr_jitter 343.890s 3146.547us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 444.870s 2786.673us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 5 8 62.50
chip_sw_sensor_ctrl_alert 984.180s 6826.783us 5 5 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 386.110s 2634.844us 0 3 0.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 375.240s 3323.471us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 0 3 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 386.110s 2634.844us 0 3 0.00
chip_sw_smoketest 48 48 100.00
chip_sw_aes_smoketest 456.260s 3223.337us 3 3 100.00
chip_sw_aon_timer_smoketest 444.380s 3634.412us 3 3 100.00
chip_sw_clkmgr_smoketest 390.290s 2992.916us 3 3 100.00
chip_sw_csrng_smoketest 390.810s 2593.484us 3 3 100.00
chip_sw_entropy_src_smoketest 1808.880s 6663.561us 3 3 100.00
chip_sw_gpio_smoketest 459.430s 3280.854us 3 3 100.00
chip_sw_hmac_smoketest 443.150s 3115.576us 3 3 100.00
chip_sw_kmac_smoketest 465.020s 3194.028us 3 3 100.00
chip_sw_otbn_smoketest 3095.860s 11417.019us 3 3 100.00
chip_sw_pwrmgr_smoketest 570.670s 5104.866us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 653.530s 5851.080us 3 3 100.00
chip_sw_rv_plic_smoketest 376.790s 2832.808us 3 3 100.00
chip_sw_rv_timer_smoketest 371.720s 2825.973us 3 3 100.00
chip_sw_rstmgr_smoketest 375.440s 2582.350us 3 3 100.00
chip_sw_sram_ctrl_smoketest 389.240s 2880.102us 3 3 100.00
chip_sw_uart_smoketest 351.640s 2899.021us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 384.780s 3341.545us 3 3 100.00
chip_sw_rom_functests 3 3 100.00
rom_keymgr_dpe_functest 804.000s 4345.067us 3 3 100.00
chip_sw_boot 0 3 0.00
chip_sw_uart_tx_rx_bootstrap 28800.195s 0.000us 0 3 0.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 5440.390s 15466.953us 3 3 100.00
chip_sw_rom_raw_unlock 2 3 66.67
rom_raw_unlock 1003.140s 13882.690us 2 3 66.67
chip_sw_power_idle_load 2 3 66.67
chip_sw_power_idle_load 742.670s 3750.299us 2 3 66.67
chip_sw_power_sleep_load 1 3 33.33
chip_sw_power_sleep_load 566.110s 9082.507us 1 3 33.33
chip_sw_exit_test_unlocked_bootstrap 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 13200.200s 0.000us 0 3 0.00
tl_d_oob_addr_access 25 30 83.33
chip_tl_errors 3600.196s 0.000us 25 30 83.33
tl_d_illegal_access 25 30 83.33
chip_tl_errors 3600.196s 0.000us 25 30 83.33
tl_d_outstanding_access 10 12 83.33
chip_csr_aliasing 10800.199s 0.000us 0 1 0.00
chip_same_csr_outstanding 5484.130s 36285.766us 4 5 80.00
chip_csr_hw_reset 1058.550s 12841.534us 1 1 100.00
chip_csr_rw 1216.910s 12562.867us 5 5 100.00
tl_d_partial_access 10 12 83.33
chip_csr_aliasing 10800.199s 0.000us 0 1 0.00
chip_same_csr_outstanding 5484.130s 36285.766us 4 5 80.00
chip_csr_hw_reset 1058.550s 12841.534us 1 1 100.00
chip_csr_rw 1216.910s 12562.867us 5 5 100.00
xbar_base_random_sequence 50 50 100.00
xbar_random 88.840s 2150.534us 50 50 100.00
xbar_random_delay 300 300 100.00
xbar_smoke_zero_delays 8.010s 47.940us 50 50 100.00
xbar_smoke_large_delays 113.890s 10743.329us 50 50 100.00
xbar_smoke_slow_rsp 124.870s 6836.802us 50 50 100.00
xbar_random_zero_delays 50.550s 562.587us 50 50 100.00
xbar_random_large_delays 610.220s 54620.028us 50 50 100.00
xbar_random_slow_rsp 551.970s 28078.856us 50 50 100.00
xbar_unmapped_address 100 100 100.00
xbar_unmapped_addr 65.790s 1153.826us 50 50 100.00
xbar_error_and_unmapped_addr 68.230s 1214.741us 50 50 100.00
xbar_error_cases 100 100 100.00
xbar_error_random 83.460s 2071.828us 50 50 100.00
xbar_error_and_unmapped_addr 68.230s 1214.741us 50 50 100.00
xbar_all_access_same_device 100 100 100.00
xbar_access_same_device 129.430s 3262.237us 50 50 100.00
xbar_access_same_device_slow_rsp 1392.250s 85816.235us 50 50 100.00
xbar_all_hosts_use_same_source_id 50 50 100.00
xbar_same_source 80.930s 2576.700us 50 50 100.00
xbar_stress_all 100 100 100.00
xbar_stress_all 570.420s 12193.527us 50 50 100.00
xbar_stress_all_with_error 744.620s 16554.014us 50 50 100.00
xbar_stress_with_reset 100 100 100.00
xbar_stress_all_with_rand_reset 917.780s 19139.911us 50 50 100.00
xbar_stress_all_with_reset_error 1129.020s 20705.310us 50 50 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 5440.390s 15466.953us 3 3 100.00
rom_e2e_shutdown_output 2 3 66.67
rom_e2e_shutdown_output 5822.610s 32968.862us 2 3 66.67
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 6115.710s 23014.046us 3 3 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 4003.030s 11094.051us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 5418.450s 17120.832us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 5345.270s 15270.385us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 5242.920s 15948.209us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 5353.600s 15549.708us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 4302.030s 11291.796us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 5732.040s 15872.907us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 5790.530s 15712.951us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 5629.650s 15871.703us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 5566.310s 15447.502us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 7448.820s 17480.222us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 9356.820s 24664.739us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 9885.200s 24360.475us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 9987.070s 24768.013us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 9476.390s 23375.705us 1 1 100.00
rom_e2e_sigverify_always 14 15 93.33
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 7825.990s 24002.374us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 8955.680s 30472.921us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 9311.060s 23272.883us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 8993.230s 23509.630us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 9656.760s 25524.695us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 4316.660s 17567.402us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 7182.450s 43968.465us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 5877.070s 27928.440us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 5199.610s 13848.598us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 4930.330s 13425.926us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 4632.720s 18442.063us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 6501.640s 28545.398us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 5294.630s 20613.990us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 5370.730s 19287.071us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 5233.840s 21255.729us 1 1 100.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 4321.450s 13549.913us 3 3 100.00
rom_e2e_asm_init_dev 5768.210s 16120.818us 3 3 100.00
rom_e2e_asm_init_prod 6066.620s 19451.835us 3 3 100.00
rom_e2e_asm_init_prod_end 5869.110s 15654.557us 3 3 100.00
rom_e2e_asm_init_rma 5612.390s 14964.516us 3 3 100.00
rom_e2e_keymgr_dpe_init 9 9 100.00
rom_e2e_keymgr_dpe_init_rom_ext_meas 10812.600s 31614.599us 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_no_meas 11073.350s 29633.627us 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas 11095.840s 29267.242us 3 3 100.00
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 5734.030s 16015.766us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.195s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.195s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 370.130s 2589.204us 3 3 100.00
chip_sw_aes_enc_jitter_en 398.760s 2768.385us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 365.390s 3133.260us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 321.140s 2839.373us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 3332.920s 13072.893us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 408.490s 2579.139us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 843.300s 4755.956us 3 3 100.00
chip_sw_all_escalation_resets 93 100 93.00
chip_sw_all_escalation_resets 930.350s 5284.389us 93 100 93.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 1070.500s 5295.384us 3 3 100.00
chip_plic_all_irqs_10 566.970s 3979.097us 3 3 100.00
chip_plic_all_irqs_20 748.000s 3707.621us 3 3 100.00
chip_sw_alert_handler_entropy 0 3 0.00
chip_sw_alert_handler_entropy 450.190s 3114.502us 0 3 0.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 2394.390s 14729.594us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 646.660s 5305.883us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 409.190s 3006.266us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 421.410s 2760.218us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 2032.460s 7981.153us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 2198.990s 7983.272us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1623.120s 8360.012us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 3 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 14400.235s 0.000us 0 3 0.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 548.640s 3845.082us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 570.670s 5104.866us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 548.640s 3845.082us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1029.640s 8449.014us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1029.640s 8449.014us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 752.840s 7337.393us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 866.190s 4993.641us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 1249.870s 5675.297us 3 3 100.00
chip_sw_aes_idle 321.140s 2839.373us 3 3 100.00
chip_sw_hmac_enc_idle 402.520s 3049.590us 3 3 100.00
chip_sw_kmac_idle 399.560s 3094.461us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 726.690s 4623.796us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 689.800s 4529.907us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 688.140s 4539.722us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 721.070s 4485.635us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1974.380s 10148.451us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 847.020s 3743.752us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 838.870s 4672.549us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 817.930s 3936.728us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 804.400s 4492.100us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 818.170s 4481.665us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 840.050s 4729.459us 3 3 100.00
chip_sw_ast_clk_outputs 1253.510s 7719.756us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 2971.880s 23110.999us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 817.930s 3936.728us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 804.400s 4492.100us 3 3 100.00
chip_sw_clkmgr_jitter 24 24 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6170.960s 18764.503us 3 3 100.00
chip_sw_aes_enc_jitter_en 398.760s 2768.385us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1460.240s 6887.658us 3 3 100.00
chip_sw_hmac_enc_jitter_en 409.440s 3261.901us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 2848.950s 11943.245us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 440.900s 3133.962us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 815.950s 4680.027us 3 3 100.00
chip_sw_clkmgr_jitter 343.890s 3146.547us 3 3 100.00
chip_sw_clkmgr_extended_range 22 24 91.67
chip_sw_clkmgr_jitter_reduced_freq 352.270s 2948.480us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 6421.290s 25312.747us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 334.520s 2721.890us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 365.600s 3208.031us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 2184.790s 11757.207us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 395.440s 2909.531us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 805.870s 4511.840us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 28800.191s 0.000us 1 3 33.33
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 1253.510s 7719.756us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 0 3 0.00
chip_sw_clkmgr_sleep_frequency 776.330s 4489.341us 0 3 0.00
chip_sw_clkmgr_reset_frequency 0 3 0.00
chip_sw_clkmgr_reset_frequency 1069.260s 9104.853us 0 3 0.00
chip_sw_clkmgr_escalation_reset 93 100 93.00
chip_sw_all_escalation_resets 930.350s 5284.389us 93 100 93.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 2032.460s 7981.153us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 1838.490s 7066.093us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 615.920s 4412.844us 3 3 100.00
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 1352.310s 8259.552us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 405.000s 3075.729us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 10348.870s 32312.250us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 398.430s 3033.129us 3 3 100.00
chip_sw_edn_entropy_reqs 1445.360s 6000.736us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 398.430s 3033.129us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 1838.490s 7066.093us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 386.410s 2689.026us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 386.760s 2895.719us 3 3 100.00
chip_sw_hmac_enc_jitter_en 409.440s 3261.901us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 402.520s 3049.590us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 3159.670s 11982.664us 3 3 100.00
chip_sw_hmac_multistream_mode 0 3 0.00
chip_sw_hmac_multistream 3600.166s 0.000us 0 3 0.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 887.520s 4856.746us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 920.850s 5649.162us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 854.370s 5886.480us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 709.120s 4576.467us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 6 6 100.00
chip_sw_keymgr_dpe_key_derivation 3324.920s 12157.754us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 2848.950s 11943.245us 3 3 100.00
chip_sw_keymgr_dpe_sideload_kmac 3 3 100.00
chip_sw_keymgr_dpe_sideload_kmac 3431.750s 12909.654us 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 3332.920s 13072.893us 3 3 100.00
chip_sw_keymgr_dpe_sideload_otbn 0 3 0.00
chip_sw_keymgr_dpe_sideload_otbn 3600.205s 0.000us 0 3 0.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 396.660s 3385.095us 3 3 100.00
chip_sw_kmac_mode_kmac 432.360s 2450.369us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 440.900s 3133.962us 3 3 100.00
chip_sw_kmac_app_keymgr_dpe 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 3324.920s 12157.754us 3 3 100.00
chip_sw_kmac_app_lc 14 15 93.33
chip_sw_lc_ctrl_transition 3443.360s 37598.156us 14 15 93.33
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 722.200s 9003.460us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 2992.510s 10317.427us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 399.560s 3094.461us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 843.300s 4755.956us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1710.970s 12949.666us 5 5 100.00
chip_tap_straps_rma 1339.880s 9723.896us 5 5 100.00
chip_tap_straps_prod 2281.840s 17061.261us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 415.510s 2843.496us 3 3 100.00
chip_sw_lc_ctrl_init 14 15 93.33
chip_sw_lc_ctrl_transition 3443.360s 37598.156us 14 15 93.33
chip_sw_lc_ctrl_transitions 14 15 93.33
chip_sw_lc_ctrl_transition 3443.360s 37598.156us 14 15 93.33
chip_sw_lc_ctrl_kmac_req 14 15 93.33
chip_sw_lc_ctrl_transition 3443.360s 37598.156us 14 15 93.33
chip_sw_lc_ctrl_key_div 2 3 66.67
chip_sw_keymgr_dpe_key_derivation_prod 3600.198s 0.000us 2 3 66.67
chip_sw_lc_ctrl_broadcast 71 81 87.65
chip_sw_rram_rma_unlocked 806.630s 10010.320us 0 3 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 576.880s 3967.647us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 1268.090s 6551.383us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 1290.020s 6420.102us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 1094.080s 5980.086us 0 3 0.00
chip_sw_lc_ctrl_transition 3443.360s 37598.156us 14 15 93.33
chip_sw_rram_ctrl_lc_rw_en 760.350s 4485.501us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 3324.920s 12157.754us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1560.210s 18042.596us 3 3 100.00
chip_sw_sram_ctrl_execution_main 1102.600s 7728.826us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 2971.880s 23110.999us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 847.020s 3743.752us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 838.870s 4672.549us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 817.930s 3936.728us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 804.400s 4492.100us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 818.170s 4481.665us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 840.050s 4729.459us 3 3 100.00
chip_tap_straps_dev 1710.970s 12949.666us 5 5 100.00
chip_tap_straps_rma 1339.880s 9723.896us 5 5 100.00
chip_tap_straps_prod 2281.840s 17061.261us 5 5 100.00
chip_rv_dm_lc_disabled 285.460s 4594.361us 0 3 0.00
chip_lc_scrap 6 6 100.00
chip_sw_lc_ctrl_rma_to_scrap 760.690s 5473.591us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 767.280s 8480.040us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 754.270s 7458.400us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 710.990s 5837.908us 3 3 100.00
chip_lc_test_locked 0 6 0.00
chip_sw_lc_walkthrough_testunlocks 3600.195s 0.000us 0 3 0.00
chip_rv_dm_lc_disabled 285.460s 4594.361us 0 3 0.00
chip_sw_lc_walkthrough 3 15 20.00
chip_sw_lc_walkthrough_dev 2249.180s 16875.642us 0 3 0.00
chip_sw_lc_walkthrough_prod 2696.150s 18049.178us 0 3 0.00
chip_sw_lc_walkthrough_prodend 2520.940s 19577.197us 3 3 100.00
chip_sw_lc_walkthrough_rma 1645.000s 14322.466us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 3600.195s 0.000us 0 3 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 9 9 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 389.080s 5858.915us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 481.670s 5688.612us 3 3 100.00
rom_volatile_raw_unlock 392.810s 3336.300us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 6078.030s 17297.442us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6170.960s 18764.503us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 1249.870s 5675.297us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 1249.870s 5675.297us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 1249.870s 5675.297us 3 3 100.00
chip_sw_otbn_mem_scramble 2 3 66.67
chip_sw_otbn_mem_scramble 660.910s 3971.685us 2 3 66.67
chip_otp_ctrl_init 14 15 93.33
chip_sw_lc_ctrl_transition 3443.360s 37598.156us 14 15 93.33
chip_sw_otp_ctrl_keys 8 12 66.67
chip_sw_otbn_mem_scramble 660.910s 3971.685us 2 3 66.67
chip_sw_keymgr_dpe_key_derivation 3324.920s 12157.754us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 852.750s 5351.785us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.193s 0.000us 0 3 0.00
chip_sw_otp_ctrl_entropy 8 12 66.67
chip_sw_otbn_mem_scramble 660.910s 3971.685us 2 3 66.67
chip_sw_keymgr_dpe_key_derivation 3324.920s 12157.754us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 852.750s 5351.785us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.193s 0.000us 0 3 0.00
chip_sw_otp_ctrl_program 14 15 93.33
chip_sw_lc_ctrl_transition 3443.360s 37598.156us 14 15 93.33
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 907.540s 5721.127us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 415.510s 2843.496us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 23 27 85.19
chip_sw_otp_ctrl_lc_signals_test_unlocked0 576.880s 3967.647us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 1268.090s 6551.383us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 1290.020s 6420.102us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 1094.080s 5980.086us 0 3 0.00
chip_sw_lc_ctrl_transition 3443.360s 37598.156us 14 15 93.33
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1627.330s 6918.936us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 639.280s 7082.006us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 304.820s 2585.342us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 337.570s 2670.203us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 879.390s 7753.563us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 0 3 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 647.050s 5210.300us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 2162.660s 22028.925us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 6 6 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1695.280s 13577.539us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1029.640s 8449.014us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 387.760s 3813.854us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 643.390s 3685.816us 3 3 100.00
chip_sw_pwrmgr_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 639.280s 7082.006us 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 633.460s 4219.362us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 3 33.33
chip_sw_pwrmgr_random_sleep_power_glitch_reset 3273.300s 30766.828us 1 3 33.33
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 662.190s 6398.486us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 346.610s 2991.195us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 664.560s 7063.235us 0 3 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1162.220s 5965.521us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1835.270s 10645.922us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2472.300s 22259.963us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 337.760s 2975.458us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 93 100 93.00
chip_sw_all_escalation_resets 930.350s 5284.389us 93 100 93.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1560.210s 18042.596us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1560.210s 18042.596us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 9 12 75.00
chip_sw_pwrmgr_all_reset_reqs 1835.270s 10645.922us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 664.560s 7063.235us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 643.390s 3685.816us 3 3 100.00
chip_sw_pwrmgr_smoketest 570.670s 5104.866us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 746.210s 5583.137us 3 3 100.00
chip_sw_rstmgr_cpu_info 3 3 100.00
chip_sw_rstmgr_cpu_info 876.050s 5474.476us 3 3 100.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 653.540s 4550.419us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 2394.390s 14729.594us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 407.160s 3176.235us 3 3 100.00
chip_sw_rstmgr_escalation_reset 93 100 93.00
chip_sw_all_escalation_resets 930.350s 5284.389us 93 100 93.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 2198.990s 7983.272us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 971.530s 4641.615us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 1000.130s 4747.813us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 404.200s 2701.101us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 0 3 0.00
chip_sw_rv_core_ibex_icache_invalidate 3600.193s 0.000us 0 3 0.00
chip_sw_rv_core_ibex_fault_dump 3 3 100.00
chip_sw_rstmgr_cpu_info 876.050s 5474.476us 3 3 100.00
chip_sw_rv_core_ibex_double_fault 3 3 100.00
chip_sw_rstmgr_cpu_info 876.050s 5474.476us 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 416.660s 3064.751us 3 3 100.00
chip_jtag_csr_rw 2 3 66.67
chip_jtag_csr_rw 2691.490s 21133.739us 2 3 66.67
chip_jtag_mem_access 1 3 33.33
chip_jtag_mem_access 2478.180s 23878.179us 1 3 33.33
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 746.210s 5583.137us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 387.660s 2954.153us 0 3 0.00
chip_rv_dm_access_after_wakeup 0 3 0.00
chip_sw_rv_dm_access_after_wakeup 357.690s 2523.405us 0 3 0.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 1339.880s 9723.896us 5 5 100.00
chip_rv_dm_lc_disabled 0 3 0.00
chip_rv_dm_lc_disabled 285.460s 4594.361us 0 3 0.00
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 1070.500s 5295.384us 3 3 100.00
chip_plic_all_irqs_10 566.970s 3979.097us 3 3 100.00
chip_plic_all_irqs_20 748.000s 3707.621us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 370.400s 2914.395us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 401.220s 2685.082us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 5440.390s 15466.953us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 744.790s 5663.963us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 421.890s 2974.149us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 417.510s 3486.536us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 425.660s 2960.653us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 852.750s 5351.785us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 815.950s 4680.027us 3 3 100.00
chip_sw_sleep_sram_ret_contents 0 6 0.00
chip_sw_sleep_sram_ret_contents_no_scramble 427.360s 3127.018us 0 3 0.00
chip_sw_sleep_sram_ret_contents_scramble 392.540s 3095.568us 0 3 0.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 1102.600s 7728.826us 3 3 100.00
chip_sw_sram_lc_escalation 99 106 93.40
chip_sw_all_escalation_resets 930.350s 5284.389us 93 100 93.00
chip_sw_data_integrity_escalation 951.380s 5073.364us 6 6 100.00
chip_sw_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1162.220s 5965.521us 3 3 100.00
chip_sw_sysrst_ctrl_reset 2040.360s 22271.175us 3 3 100.00
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 393.730s 3357.244us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 2 3 66.67
chip_sw_sysrst_ctrl_outputs 380.850s 3344.106us 2 3 66.67
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 638.600s 4094.914us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 3 3 100.00
chip_sw_sysrst_ctrl_reset 2040.360s 22271.175us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_reset 3 3 100.00
chip_sw_sysrst_ctrl_reset 2040.360s 22271.175us 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2 3 66.67
chip_sw_sysrst_ctrl_ec_rst_l 4823.020s 20459.650us 2 3 66.67
chip_sw_sysrst_ctrl_flash_wp_l 2 3 66.67
chip_sw_sysrst_ctrl_ec_rst_l 4823.020s 20459.650us 2 3 66.67
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 796.990s 6154.482us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.195s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 296.820s 2664.667us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 361.530s 3308.664us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 577.950s 3695.027us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 679.550s 3641.007us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1980.150s 7942.098us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 9720.700s 31941.744us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 3345.830s 12487.952us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 337.830s 2822.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 425.950s 2526.621us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 2 3 66.67
chip_sw_rv_core_ibex_lockstep_glitch 286.080s 2400.537us 2 3 66.67
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 0 1 0.00
chip_sw_coremark 18000.184s 0.000us 0 1 0.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 2083.730s 6493.299us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 111.700s 1932.838us 0 1 0.00
rom_e2e_jtag_debug_dev 132.780s 1664.640us 0 1 0.00
rom_e2e_jtag_debug_rma 153.050s 1862.290us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 171.270s 2581.742us 0 1 0.00
rom_e2e_jtag_inject_dev 105.670s 1747.856us 0 1 0.00
rom_e2e_jtag_inject_rma 148.120s 1908.598us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 67.670s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 3 0.00
chip_sw_clkmgr_jitter_frequency 590.240s 3553.953us 0 3 0.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 632.040s 2817.257us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1794.040s 5649.486us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 1685.420s 7104.538us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 527.200s 2608.343us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 600.340s 3242.160us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 2 3 66.67
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 610.220s 5340.740us 2 3 66.67
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 790.880s 5149.907us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1835.270s 10645.922us 3 3 100.00
chip_sw_rom_ctrl_digests 3 3 100.00
chip_sw_kmac_app_rom 722.200s 9003.460us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 111.700s 1932.838us 0 1 0.00
rom_e2e_jtag_debug_dev 132.780s 1664.640us 0 1 0.00
rom_e2e_jtag_debug_rma 153.050s 1862.290us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 3 3 100.00
chip_sw_rv_dm_access_after_escalation_reset 757.350s 5237.363us 3 3 100.00
chip_sw_plic_alerts 93 100 93.00
chip_sw_all_escalation_resets 930.350s 5284.389us 93 100 93.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 7200.201s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 7200.201s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 0 3 0.00
chip_sw_spi_device_pinmux_sleep_retention 412.440s 3400.716us 0 3 0.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 780.320s 3876.270us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 5097.040s 18542.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 22 13.64
chip_sw_rstmgr_rst_cnsty_escalation 78.880s 10.300us 0 3 0.00
chip_sw_otp_ctrl_rot_auth_config 178.570s 2854.259us 0 1 0.00
chip_sw_otp_ctrl_descrambling 390.350s 2536.363us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 322.680s 3148.329us 0 3 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 15.489s 0.000us 0 3 0.00
ate_bootstrap_flash_erase 1389.520s 10010.260us 0 3 0.00
ate_bootstrap_one_frame 10800.202s 0.000us 0 3 0.00
ate_bootstrap_disjoint 10800.210s 0.000us 0 3 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 90 test runs
chip_sw_alert_handler_lpg_sleep_mode_alerts 48217857345196346488838184147510810908843040102868763533496791220921098594564 373
UVM_INFO @ 2914.980456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101080645963702003895562662975604903431877649682025561303720067188644005376779 373
UVM_INFO @ 2635.868000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84433943548504766204300727632245233902283563617636354559076526321098075158515 373
UVM_INFO @ 2270.647372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19218756742880219291445880130685993347528288705426932557871869718525125187091 373
UVM_INFO @ 2688.174800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78676506072542397605194839280370710716377833791937506658029026254293642526723 373
UVM_INFO @ 2961.001777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30483064050483278907506070748755816778816926065324493473516834058675769407453 373
UVM_INFO @ 3109.875986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 111951645414843309311199492707629041001652750397878595914479387876143278624512 373
UVM_INFO @ 2363.855642 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107709250796968887910589521281916307658504940286070653629171916715986122339741 373
UVM_INFO @ 2259.467996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107456854312225300382442064555078147647768749226050696554605885820101129148835 373
UVM_INFO @ 2524.711546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 92077023768764406725205970703019444823581952581090973456280538560029711886465 373
UVM_INFO @ 2551.843537 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 76926082792760011504272839744885719173389142889472792146452138749806212012089 373
UVM_INFO @ 2564.685335 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42604024695126339420956032236194620765052555778241257121515479375996775246721 373
UVM_INFO @ 2483.172760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49538798247105063216649832049475970226536496924387122135502018961452723940577 373
UVM_INFO @ 2514.823032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40646496979728617380278338109264951448927381947816344263716914206246076442076 373
UVM_INFO @ 2516.883878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28177571660551820480758966475615010815659235799448333502438495987244395172744 373
UVM_INFO @ 3079.751639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34595668978678439948781487530463739207062755665315630405816297476312568439568 373
UVM_INFO @ 2535.839172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42058867210668728649619404208490544145489809300187864901496016196397553272078 373
UVM_INFO @ 2399.227563 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 20299942466087419590505212738627148618424832003006170915344893472720553428361 373
UVM_INFO @ 2613.662696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 26874277492619099190683823916513922855260937803346801636735875575042409946568 373
UVM_INFO @ 3303.275573 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 73085950119664916107761400628320587010030588881394027900950855019966133089648 373
UVM_INFO @ 2831.923512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3760998372291583487922024603589501323164518406694475942837341587279290102131 373
UVM_INFO @ 2676.827796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108299861759579509995905495811172631575569242564948134503171122878232288542067 373
UVM_INFO @ 2501.364790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 92290938547719293416030440512010577765756889361866849926012733115080611645929 373
UVM_INFO @ 2359.439880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 51692008917704717250413485363678720201009062602569169954488468261624245225396 373
UVM_INFO @ 2706.470507 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 4858680584175363748184928853336703433754877995515411863257993294101876686264 373
UVM_INFO @ 3006.266382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 83836796516001685343710621275855158672226368825044118003703257360568047546930 373
UVM_INFO @ 2355.763406 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112947422014420484254108515779583140622554692500091404733482076895981472882859 373
UVM_INFO @ 2400.179430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107739189398537460112187965726513316782837190918617772625818354896362935446943 373
UVM_INFO @ 2724.009928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 92241095117873412676012492303474030179852655219634868029552842468097247196571 373
UVM_INFO @ 2416.382790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 99560575688748875434920649114464640828897928237970928254356805445610703830349 373
UVM_INFO @ 2262.834450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 73223530402467367119377119895635650053655043634591464409630391358549810375972 373
UVM_INFO @ 2391.223823 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109375042347161833156510588252161376907112667710145356340003141970286504225504 373
UVM_INFO @ 3338.213646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71168609079675493675434046398750230202274295315048779231868613274478593948848 373
UVM_INFO @ 3214.453376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14206523243633925741104566012381556958629027732344350030023232036722364566923 373
UVM_INFO @ 2753.690629 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 87280374357227824762803341873947175401799717532373223960293741625895802458298 373
UVM_INFO @ 2549.488680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 29617561800415966109233665352319094179116721968560809901611100946218033261233 373
UVM_INFO @ 2477.746720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 98348216855860948001921359939219010141193908364646681994823521268715533014404 373
UVM_INFO @ 2583.107087 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 54455141770777941408393387203744332698425029354746912060949831254903825287505 373
UVM_INFO @ 3288.863366 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19577239103195631880360059481224873035200185752266954580823732759150109974690 373
UVM_INFO @ 3032.736924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109095856696410109255081457866512921782806596381027457462828677361521696677253 373
UVM_INFO @ 2121.803635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 87568868342868897515246102167226787900446818123999182077601812946294695494857 373
UVM_INFO @ 2798.932480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 63716906121919281025876117741236253680993493377940379960340448394997424186637 373
UVM_INFO @ 2785.454652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 12292646639698992734928749802408781685144587673462707823087234995139840611509 373
UVM_INFO @ 2830.740780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 67446591368437094027322935955579909840416266798913717796798438351013882522147 373
UVM_INFO @ 2492.778496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89598397866721864399472160555980880482324125445523819594093784472439781995600 373
UVM_INFO @ 3028.473283 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49506659189537111827661432738304763927148864893701478274768027569142743010536 373
UVM_INFO @ 2535.444258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77924185191300529753038336139158388121846931923314825010020116167385424924569 373
UVM_INFO @ 2915.419584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 24942726345779940261131002839091346802799517584098212819652758141674643140761 373
UVM_INFO @ 2329.908780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47705200361299940525139229560515957846510733589983212110663868068227859759312 373
UVM_INFO @ 2574.387398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35685362704478800444217020994017960527831882038460042832092984216348403084065 373
UVM_INFO @ 2545.950296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112803104905619094246799913686196107774767358676294205300461356095240310864476 373
UVM_INFO @ 2747.622064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77313604422068823694715111676147530006901752048570277791822771345732564496937 373
UVM_INFO @ 2812.129522 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 17339352198579256499585083644948841628678363463400296716332634358700479060342 373
UVM_INFO @ 2721.243881 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71474545269234332763329785473235670470603625433215210004557488313036467563763 373
UVM_INFO @ 2567.106645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 86586081560193215440197584236720584521734892431730873712785877242858251160850 373
UVM_INFO @ 2705.574926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 60007014484276174685220642711490634994820217421121781911077415315391403629314 373
UVM_INFO @ 2141.220075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 95602530818954688029507314072421644216919881890784487626644364111925589921488 373
UVM_INFO @ 2504.249929 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 24351072024527101364193089490130149924079915114595356752678158483730976551016 373
UVM_INFO @ 2688.071640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97857236702832533760176469850225211813249103816777800456856212581997022639968 373
UVM_INFO @ 2212.310300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 100305743487017346576141066728481975121259788880075261479257639363681532925995 373
UVM_INFO @ 2436.785044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 51447519359154651297999758429684675475640371130342699186535713357031921088701 373
UVM_INFO @ 3136.394904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 18314135985681189375699204192665498661819540913502083465366662367387591004331 373
UVM_INFO @ 2309.663700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 15851434451027599727217958801450242312716718914421489700937043955515106476311 373
UVM_INFO @ 2595.779412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 37793944639798200824117010653551834160323946635542804139614207222514706346302 373
UVM_INFO @ 2636.273211 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33664679052094960834575437063005788316461150474937424531338200908529672337556 373
UVM_INFO @ 2757.705205 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46588659017533624765445170987083667116723418787472412823512910798082260810082 373
UVM_INFO @ 2380.237940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 8114274195404933374570751391609239828769715602253091205636920755723691870322 373
UVM_INFO @ 2231.820856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77641851937916281562642406548360948787731933060330359352099258718458130033230 373
UVM_INFO @ 2969.555508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6088072205679895491012771482032378596524932562764160816984826818888106043748 373
UVM_INFO @ 2272.399028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71787164940295767860238984219766953865217107125410163633119157325265119113038 373
UVM_INFO @ 2542.238640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48015941517842641767859311149880563600962471955927716061728516753496076119238 373
UVM_INFO @ 2273.567415 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 83296460075539942150171937944676129646727765404887297621008594623121160190232 373
UVM_INFO @ 2577.324526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 31220042845483770274219521181882165303961588670102293343373947625391248384993 373
UVM_INFO @ 2476.702836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 64935804026435126864869484573092232950079158193702078674842243636977662076070 373
UVM_INFO @ 2725.737122 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55093454669887109784029225316455840553075760988709234915725909651142883155657 373
UVM_INFO @ 2587.455900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3119969986223021880676152815861753770760543790691603113811441632849701784429 373
UVM_INFO @ 2859.021076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 51481753316221717982706415708154119674453333681384682797417022648100240065848 373
UVM_INFO @ 2586.874638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33868130020047045022395980934189324113125379937426574881123997731235803680447 373
UVM_INFO @ 2901.402101 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34310892175139031285740636013157221103913065420792761058303209554814570847477 373
UVM_INFO @ 2310.280250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 9746165316103642847309749885290540946562320972687369839771797734861035559042 373
UVM_INFO @ 2770.013336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 22901051686561283178459206620262301462696359001105102863246284308093167620436 373
UVM_INFO @ 2904.697568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77225358226018935958888754357294301110387919010567646489469621380503053355596 373
UVM_INFO @ 2392.492592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 32072090897404862016313373312452699220739482266845761004707428587698851277687 373
UVM_INFO @ 2760.564228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 94287300596748399247247096238020378172376165877305115922828478108788596209380 373
UVM_INFO @ 2932.923368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14477072688785659631741727374722986929912639472040317587797296401671948572885 373
UVM_INFO @ 2736.491003 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96793489449897445351693543549278948907122312355794625365278597503008383239223 373
UVM_INFO @ 2697.485656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 11218089808362215790261638592558966520533519349100179102544741320657930132377 373
UVM_INFO @ 2398.901322 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71426879855033035738819043980185402644717667635085023060947250108148261545754 373
UVM_INFO @ 2701.126084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 27625893804553406683586953488487161893221918097107655810117915253039417057934 373
UVM_INFO @ 3013.257742 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 58899738082303009800776700132428740063724156340483045199257760263025573990281 373
UVM_INFO @ 2351.456636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error 45 test runs
chip_sw_sleep_pin_retention 3021774620797378741879905313489777318951218701228310593459471872498060918970 379
UVM_INFO @ 3315.388674 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 89047453249730835567558808890437253749743469384000357045642560679085675818804 374
UVM_INFO @ 3230.652114 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 88229333506462786223304495472711125699246966487113695930109705530065236677319 392
UVM_INFO @ 7063.234644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 16752258438744014053008106391744575246526562942713437884289092896332226777368 377
UVM_INFO @ 2487.972436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 54858404102455334188362846023956236411533056562409890450141039347509677485649 388
UVM_INFO @ 4749.841638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 50195938350380225943923348181041027767041445321969185675914012818677572831271 406
UVM_INFO @ 8373.872876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 37895362033405275866681533784443585533953320567680681360529715114253595532256 377
UVM_INFO @ 3127.018452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 83350679894882310636298384362683185976056358895283166679492973267205363626014 381
UVM_INFO @ 2637.785784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 53414184631829656189500637202565686779053646206854518390455913837099386982536 372
UVM_INFO @ 2634.843810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 78673795118395005838968212785076868765268804323337584831215637622167400008113 407
UVM_INFO @ 3938.731384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 25331369891224874505484587772460045916777508331278054585886547413597952386546 374
UVM_INFO @ 2670.202632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 11958580974004919415957346055804974596184062705947988023224459179922461312362 372
UVM_INFO @ 3148.328664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 84139366766271364032452478022036684631117642286888987982305797030553872747468 373
UVM_INFO @ 2585.341818 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 46513125526781782440039529476122317923741470600409409406807738190679597281124 390
UVM_INFO @ 2911.114704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 53672807666182663086939146466361166290962494704748324139327775734967262144012 387
UVM_INFO @ 3459.696700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_wake 92802150096726542813799873775897278416689858593041375396407226150391456107866 382
UVM_INFO @ 2794.323680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 92470983993731362287228812958533059138357513684726251207292501654694655661814 379
UVM_INFO @ 3100.654044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 83584850693498563831220735129853278686211511923127431466981519732297017854408 374
UVM_INFO @ 3400.715916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 54152653321176815635990457129571537857306567570701625625295100756038535791309 392
UVM_INFO @ 6568.260844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 16555155616745866394318851131861812663985881804990397364774109977011828412941 377
UVM_INFO @ 3951.321426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 36847311531127890881387467467147630506593667917200766238455944897469470405790 388
UVM_INFO @ 5210.300011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 36084309952414578300444992875766853788403507155490424808224962719247799271977 377
UVM_INFO @ 3330.642604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 73588403772449985286243600995694929661628140060742053453540331534192764273940 381
UVM_INFO @ 3095.567832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 109316511936352892089958193699004638352836036042481654020802697542631918124293 372
UVM_INFO @ 2043.291612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 43001268065607364091872554028867419319915688675766438545825602863257834819608 407
UVM_INFO @ 4489.341414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 95227922127133362568291635572301744117077711846682933540593311810647913494788 374
UVM_INFO @ 2311.546468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 103901172905852162772060335573217099876766820383568303462440503918591093527702 372
UVM_INFO @ 2458.156924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 55461589654433798565120161131268896160548255518041388377142577037352565113833 373
UVM_INFO @ 2596.872680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 58925356036427311572407012509266296455707312134521106183809892120547079549160 390
UVM_INFO @ 2523.404520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 30605634367293611066652861869656408656144561721356800526228360028497015046407 387
UVM_INFO @ 3768.095786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_wake 75634979753560147122111641143910112055447628802627873058350719668397162792004 382
UVM_INFO @ 3419.216032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 110290545846800757723548880452899971879679846798614872175936462875393363111084 379
UVM_INFO @ 3329.155180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 56012619460338056431827802906494213798727851926548171185351888787001930414947 374
UVM_INFO @ 2941.286376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 87501999073123574810747444026953049613341524435454501060396184561222040933295 392
UVM_INFO @ 7590.838296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 105315095157473574794932630366324738319019881122184892080451674863663740679083 377
UVM_INFO @ 3813.854240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 50552652805749778785268704308016133851788723550639977039825720968103107955001 388
UVM_INFO @ 5232.025700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 85897510291312447208854808209404641396450560536107194728765649836502861875048 379
UVM_INFO @ 2958.975208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 80591121486102987970372535717371287592844832756589761065736033350506794660765 377
UVM_INFO @ 2668.451796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 86809664323886338801261375285939637567292073773454427759536758372773246643492 381
UVM_INFO @ 2913.163376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 107104643304791957172593925369372835134616836358134801114464575502644274901228 372
UVM_INFO @ 3070.256560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 63368939233593280567136247513306014125063062319823216375720926261651632822773 407
UVM_INFO @ 4504.162956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 112919800008788608185622099284947528092860521320942249397200307039431737512255 374
UVM_INFO @ 2704.958246 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 48220747972910763101514589204005992588996304258804038615949022252775533172524 372
UVM_INFO @ 2736.399804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 98492705031103726799860826522330295428426037404011885157027072334350132728193 373
UVM_INFO @ 2711.523382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 109021045268063730698592875687235428791033606188416988582864726881557476748134 390
UVM_INFO @ 2404.831666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 40 test runs
chip_csr_aliasing 49695916380321082801197592125584103599624043377789512736822392459661790670391 None
chip_sw_uart_tx_rx_bootstrap 111588022901404688089482988318084118362055731939100179598524313805180815746456 None
chip_sw_exit_test_unlocked_bootstrap 1601361694537488990828827898143636090141944023265118578440072835674472521068 None
chip_sw_lc_walkthrough_testunlocks 102438422969823042755848037128461261894599141529338138049995584493338345438922 None
chip_sw_rv_timer_systick_test 98453848904014948256954266550585311937135453416079689945781326720139164388309 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 11508253483355221582308317957785742905054753779936241363570406963011500636496 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 35410808083767995587071143660665380598191836144728997510523134669553707827388 None
chip_sw_hmac_multistream 56437914365227601948447543838971145394747081883597074228925031909653807000627 None
chip_sw_keymgr_dpe_sideload_otbn 77978203890025535257186781381291557314774014810855464227110312682025874643859 None
chip_sw_coremark 75971605131389376712800815530144899184815858355891444242761919326026786949813 None
chip_sw_rv_core_ibex_icache_invalidate 50645834706169526244163793016165451645514437111086209799546534410563571091668 None
ate_bootstrap_one_frame 6167199483690711132416052086869777228902593254357906723463205638873092009181 None
ate_bootstrap_disjoint 22274642563225829684323033097622579862666049281194126515488939762452633850177 None
chip_sw_uart_tx_rx_bootstrap 66638043463959637142619042867047910737549204062519710928731149118503345434382 None
chip_sw_exit_test_unlocked_bootstrap 51951256313221962981063151559559492056589992780263917679990459107186639390839 None
chip_sw_lc_walkthrough_testunlocks 69416139546277970004518336814271911818969018492614692717206427814928634447461 None
chip_sw_rv_timer_systick_test 97284456952330299306260992517033188631773873050157009509672767011641307711888 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 93555852085424788753972636997706453383625595529884272607454079961204151609530 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 26708422426911680733531095578106083610369504678918987660357751633004134501805 None
chip_sw_keymgr_dpe_sideload_otbn 34719512794558408849447731138902888114563522134542293252524318108457695232034 None
chip_sw_rv_core_ibex_icache_invalidate 33627214710253620174357376108314766436418661209712313005359276981336415402303 None
chip_sw_csrng_edn_concurrency_reduced_freq 10313769510201848235031396797702494642867502540279567947183882368680238655520 None
ate_bootstrap_one_frame 111967445488232562638148832565466411491011244283053206298265204926286611551998 None
ate_bootstrap_disjoint 55247660341648536749006536386675281334549357068506931616697210583732451249465 None
chip_sw_uart_tx_rx_bootstrap 43405161665954410704533059852469952848463208208020018899788785871856393663266 None
chip_sw_exit_test_unlocked_bootstrap 94877578019159424691298220153261690885536118474057330652451703179039511197761 None
chip_sw_lc_walkthrough_testunlocks 88511666519533515350104040131419144965173533150228214500643012494619642484510 None
chip_sw_rv_timer_systick_test 6025906474829449832033045111727011407764653692780003635003765994630613340556 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 57191611300578733650888838123250703907999600200146656044686971317546199817219 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 95232258483964789019628076657238965163358196891834762872654416005056303279738 None
chip_sw_keymgr_dpe_key_derivation_prod 34332490119053733674295969845440886066013883050444997554350372502402180816677 None
chip_sw_keymgr_dpe_sideload_otbn 40785865667256731729470621605560681022024443610689967164290487883171236251082 None
chip_sw_rv_core_ibex_icache_invalidate 66093781762811480445970681864535458012868598846089662971905452811924300219076 None
chip_sw_csrng_edn_concurrency_reduced_freq 46459832329315831219358324154498741859255809239182158905077314363272821958820 None
ate_bootstrap_one_frame 7954930542297335895926998128526333795687237902315034748840472190415162687724 None
ate_bootstrap_disjoint 16207912529107852445430397276599040107929079354948447945229162787106901076272 None
chip_tl_errors 115071412003349986967966797781170815228136318260595227830942980179602744909333 None
chip_tl_errors 11847040128479813324079656821402486749969129447320940809648674267903951211220 None
chip_tl_errors 52930034400446428071116402563612790619977604266934014237999220058971994281804 None
chip_tl_errors 62294556502958132932966036386506055189428197610879480227581187283621120119179 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 9 test runs
chip_sw_lc_walkthrough_dev 60796386097031384590933561469319502749731367505091366707899120719631238979320 433
UVM_INFO @ 16008.658810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 111404760154987318105591839875417302334636490170893516070970531350387563749866 433
UVM_INFO @ 18049.177856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 52358991403448719715724938555353458366676633636538748315476748531434688233824 405
UVM_INFO @ 11769.825748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 82730673551150949879299224860915676592249303993133965633827268226978548376837 433
UVM_INFO @ 15078.340980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 24798809448627825000407001073344440306730730498195808167557920020060775586870 433
UVM_INFO @ 18012.505241 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 65801057713549396138788299874744562650140945644239751691238059543217557887153 405
UVM_INFO @ 11100.806520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 61522395347885462858954896609090887381711304746973335909921952827363259794915 433
UVM_INFO @ 16875.642031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 31938437866593649146923331652631492400964263785406035818545013651524490804631 433
UVM_INFO @ 16995.367192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 31768822751649173062236120460076065120683031029257569076697201549969981699126 405
UVM_INFO @ 14322.466016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 7 test runs
chip_sw_otp_ctrl_rot_auth_config 2306064389724147389351380223047408026469674037154356607776655524291190564278 381
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 99287808874452335430939676639781753420519502115499741440710849858764898093151 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 38466604802440138261346200762594985791786518623410894742524336465516278246173 381
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 40079349323311334379485449932477675181517216886159213618232858256427346645834 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 102927170061413283072709547176775750494670276493415480975901317965150719565094 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 33801376819727858146470211791707939218238525363759130652903846602360713734367 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 32437436917646176869580692965738687668318109767302526269594951828272895256404 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 7 test runs
chip_sw_alert_handler_lpg_sleep_mode_pings 104785882568388257055708004075232360855671318072184922771082924728912623221867 373
UVM_INFO @ 2312.939016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 24197919575796550834325239659823477056935841086031089822235738759804030929350 461
UVM_INFO @ 3114.502421 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 17412697450913899923188787356861246829439382871569869583001537062593052223395 377
UVM_INFO @ 3750.299176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 26194002833027187231147597308144275891368344857369503181086405959325181336144 373
UVM_INFO @ 2474.957352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 76328792898925553625159789922814041922127648888588562959771093255862834983374 500
UVM_INFO @ 3101.879130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 94305342972634406521361475829437081003104628579594015577387127544042694140436 374
UVM_INFO @ 2760.217656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 27142925540541742227941386385347308996031939151930102360600287985111915190872 476
UVM_INFO @ 2836.694684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 6 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 53805720886142538086702308852081842035976348005719697938053028274732649977601 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 90334244843015471538326954841214370452757746800055444009527922993548231726514 None
---- STDERR ----
Another command (pid=195332) is running. Waiting for it to complete on the server (server_pid=195394)...
Another command (pid=197948) is running. Waiting for it to complete on the server (server_pid=195394)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 35755290689310142335246439553641733636790545692957090304283075082779416306982 None
---- STDERR ----
Another command (pid=231743) is running. Waiting for it to complete on the server (server_pid=195394)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 9276435429992197678706457542857730527334978351033536806130179373733163392698 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 75942050440414910802748081613243168705383357599432108579859679014268854875007 None
---- STDERR ----
Another command (pid=1168486) is running. Waiting for it to complete on the server (server_pid=195394)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 19397084760740205433924927942619353366008978699794524094133288246684443398598 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 3 test runs
chip_sw_rstmgr_rst_cnsty_escalation 29755795047657005706591613994567776333918938693301667225319315132104651289560 365
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 30452602010594794813885918856880900869976582989422196331540163268505676332391 365
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 9159114601394657124576878951566699042063321506844765875518683939479509125585 365
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred! 3 test runs
chip_sw_rram_rma_unlocked 44984950948070826296221813253062479413979739337838733747630731107827055440363 337
UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rram_rma_unlocked 5110925110344091893314194139270015313338096888040583991449852010588890220912 337
UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rram_rma_unlocked 46222599368152160850182556106708949785429854596894650414366917253654304147115 337
UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 3 test runs
chip_sw_otp_ctrl_lc_signals_rma 62059436265461972667707425532971438064232324682952167236650689680812953533296 404
UVM_INFO @ 5980.085514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 64727305333736947697440252315069574109611577809938788165264033390089932384796 404
UVM_INFO @ 6595.971044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 98626061464180864957255988127683008320537963463373709067785589319752489459959 404
UVM_INFO @ 5312.942968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 3 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 102827356739993734533556725017874755628385181842049833868762533802134871285042 377
UVM_ERROR @ 3039.576284 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3039.576284 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 62956463714717089608213598479417756918243253352858473886029959750402311119905 377
UVM_ERROR @ 2991.194846 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2991.194846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 72668308633458947645166412773996504334800988783866506577308984810631555483522 377
UVM_ERROR @ 2466.939854 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2466.939854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state. 3 test runs
chip_sw_clkmgr_reset_frequency 14070813974775720948234242346799399157220993501315123500950670185841897534676 400
UVM_INFO @ 7628.769228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_reset_frequency 8600711624919123814759294065219765830750390391115833146374289318003539875622 400
UVM_INFO @ 9104.852856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_reset_frequency 115725658285099750087308885659045796005580165394672288497270562392834107690300 400
UVM_INFO @ 10202.273316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_clkmgr_jitter_frequency 27097788385008709408199147581234096160315672223762193686975448088530858532439 407
UVM_INFO @ 3553.953499 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 93163840645519322711400103025666469766148481432873024010003009831104536680855 407
UVM_INFO @ 3383.282281 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 72868684047476728528206595658661730692864620694792825766693751681895020591943 407
UVM_INFO @ 3386.806032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 3 test runs
chip_sw_ast_clk_rst_inputs 96429471356139592842870480797405068476741238362928603157622394729385834616886 391
UVM_INFO @ 11591.691558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 71893585519452425978530936135222663637067706409401694780576198675308881767517 391
UVM_INFO @ 13336.395875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 104684849319214387228379679721312383960686908319516169665094091902724632187921 391
UVM_INFO @ 9232.561365 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 3 test runs
ate_bootstrap_flash_erase 89143000150289167506233828792796370434741967896283254919534201297188130903283 339
UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 52104913027372709738237165782170548827325116947235625901924711336903888847511 339
UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 10460671103189846000731189214267348004666654371102330319071568128349171725020 339
UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [*] vs * [*]) 3 test runs
rom_e2e_jtag_debug_test_unlocked0 30952252722462151767772132063996199001273210486886825863943911256386607685037 359
UVM_INFO @ 1932.837500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_dev 1055263970268270464788466112229135509928849693505727938871327161321507098928 359
UVM_INFO @ 1664.640000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_rma 67475142885347600231730359651316403370211322474501521722024324671571412558732 359
UVM_INFO @ 1862.290000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal triggered unexpectedly 3 test runs
chip_same_csr_outstanding 9402618840435445398493161595270239888790996343123260665549837086944798049404 290
UVM_INFO @ 15608.076984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 82957283208503431365366722749105890487520145650362825877838492419405696521448 382
UVM_INFO @ 2517.198180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 64093657849398137337676706262877776307362239042261462645992542287722706438088 382
UVM_INFO @ 3430.515892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 2 test runs
chip_sw_spi_device_pass_through_collision 34053630782431449715033035050381043087896852551095571614860379244574422350741 391
UVM_INFO @ 2620.179784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 2688710057297925629323303946724648128039713085737575935833028352340185883242 391
UVM_INFO @ 2974.148802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(buf_intg_err == '0)' 2 test runs
chip_sw_sysrst_ctrl_ec_rst_l 60821807546289464379949638134388112604671973263119389808389773501464370389963 390
UVM_ERROR @ 20089.987648 us: (rram_phy_rd.sv:697) [ASSERT FAILED] IntgError
UVM_INFO @ 20089.987648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_outputs 59229906913046446775244326180755204151226853738194929617176896105274327910969 379
UVM_ERROR @ 2712.371904 us: (rram_phy_rd.sv:697) [ASSERT FAILED] IntgError
UVM_INFO @ 2712.371904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [*] vs * [*]) RV_DM sbaddress* read back check failed, got *, expected * 2 test runs
chip_rv_dm_lc_disabled 110785444748858118068610525845515588126467246436805903187861983734113484701741 292
UVM_INFO @ 1862.485770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 51614103280309249487766054375163671366260596456289773305047103722835943522391 313
UVM_INFO @ 4594.361195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' 2 test runs
rom_e2e_shutdown_output 93840638115316716231435936047484047130932191045641818054797861648457985897989 393
UVM_ERROR @ 12131.434668 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 12131.434668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 6770290691590929067869029737962340128213928544480811112358048625133338031763 457
UVM_ERROR @ 25524.694584 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 25524.694584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 104140204965863926144491047742989744675873130686476120155299132986809377850818 425
UVM_INFO @ 12010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 45430782810174120479096189495485186951450432229354982053843807324556887034846 435
UVM_INFO @ 12010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts! 2 test runs
chip_jtag_csr_rw 107845916801608323175863111607435342246317757516552965718563715379427120934388 5365
UVM_INFO @ 2602.470896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_jtag_mem_access 54773176399316879386745635432454591066789554808843390739495513649055555168276 5365
UVM_INFO @ 2381.223288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:614)] CHECK-fail: Unexpected mtval: expected *, got * 2 test runs
chip_sw_all_escalation_resets 65818958128193890270099342951171526268711996092525254145126471118619860420013 383
UVM_INFO @ 2965.653368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 43750276061011484378187501715522972243854360516155505692084370493359978385425 383
UVM_INFO @ 2240.032880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1072)] Unexpected fault 2 test runs
chip_sw_all_escalation_resets 77490773040059111555370056721252099931204868631891806858865525010523995658830 375
UVM_INFO @ 3186.874510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 13412262958160113521780895594860372521882247256167495371677308674454026840540 375
UVM_INFO @ 3254.020148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:715)] CHECK-fail: Alert handler NMI state not expected: 1 test run
chip_sw_otp_ctrl_escalation 17664442025477400841878523972472129353004619221898775863368531212442472144667 379
alert_enable:1
alert_raised:0
UVM_INFO @ 3242.159805 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:340)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 72524146013487997189462722236293771145525552844461596730216973449685551627696 371
UVM_INFO @ 2550.097868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:221) [jtag_riscv_agent_pkg] Check failed sbcs_val[SbAccess32] == * (* [*] vs * [*]) expect SBA width to be * bits! 1 test run
chip_jtag_mem_access 38088875419824798578978849424856956959194740688630532399823577536024942907576 5365
UVM_INFO @ 1574.807359 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 23487494148857479811963137939907566253150758174774565800290464185712273808358 388
UVM_INFO @ 2062.458124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_if.sv:154) [tb.dut.chip_if] Detected an X on MioPadIoc* (num=30) 1 test run
chip_padctrl_attributes 32359332464301172592482643104801364912335625038250743234891701707302669947830 351
UVM_INFO @ 1874.298553 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 1 test run
rom_raw_unlock 26859431844135424919895832673549097184145334925908090470488342100077228913373 384
UVM_INFO @ 11152.740475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:385)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 30140410860615372009017134547981109304453499116112469164834288565742171925369 371
UVM_INFO @ 2579.139092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch 1 test run
chip_sw_spi_device_pass_through_collision 31305153232790015436672302537775860567480397176749582965160245655328348106397 393
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otbn_mem_scramble_test_sim_dv(sw/device/tests/otbn_mem_scramble_test.c:255)] CHECK-fail: Expecting at least * IMEM integrity errors, got * 1 test run
chip_sw_otbn_mem_scramble 100965070245872342020105486354497161152550520871821999206106732905317806260354 374
UVM_INFO @ 2995.773076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:310)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 79637017200990021651043144249160394950816949580638445767684345431150334474232 371
UVM_INFO @ 2627.520721 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * 1 test run
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 105681222311823281421424721553698391046025213277691381162487644398068738885016 380
UVM_INFO @ 5221.693375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 106794546120516461667108565184905950731027366142563494901002203353248347075464 292
UVM_INFO @ 1835.375663 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_transition 4460537681158818639245369616962536379995131009746668506628018414130059822048 411
UVM_INFO @ 37598.155561 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:198) scoreboard [scoreboard] a_source: * & d_source: * mismatch 1 test run
chip_tl_errors 99960471453640748110891776245127270818667585968051293512046424023121917403018 282
UVM_INFO @ 2109.118231 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_all_escalation_resets 42096249470035366245826386094940979742880571006393368096338511905906422761649 383
UVM_ERROR @ 3063.827714 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3063.827714 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---