Simulation Results: clkmgr

 
12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.39 %
  • code
  • 98.87 %
  • assert
  • 96.47 %
  • func
  • 87.82 %
  • line
  • 99.29 %
  • branch
  • 99.06 %
  • cond
  • 95.98 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.31%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.400s 85.496us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.040s 40.614us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.400s 141.404us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.070s 408.915us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.240s 35.190us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.090s 264.680us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.400s 141.404us 5 5 100.00
clkmgr_csr_aliasing 1.240s 35.190us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.160s 56.402us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.820s 168.586us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.470s 100.070us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.470s 68.070us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.400s 85.496us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 13.110s 2389.711us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 22.210s 2415.082us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 13.110s 2389.711us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 46.680s 11340.171us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.260s 55.385us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 4.400s 50.799us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 4.400s 50.799us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.040s 40.614us 1 1 100.00
clkmgr_csr_rw 1.400s 141.404us 5 5 100.00
clkmgr_csr_aliasing 1.240s 35.190us 1 1 100.00
clkmgr_same_csr_outstanding 2.000s 238.372us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.040s 40.614us 1 1 100.00
clkmgr_csr_rw 1.400s 141.404us 5 5 100.00
clkmgr_csr_aliasing 1.240s 35.190us 1 1 100.00
clkmgr_same_csr_outstanding 2.000s 238.372us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
clkmgr_sec_cm 6.040s 1429.682us 5 5 100.00
clkmgr_tl_intg_err 7.590s 1389.566us 25 25 100.00
shadow_reg_update_error 20 20 100.00
clkmgr_shadow_reg_errors 3.980s 500.099us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
clkmgr_shadow_reg_errors 3.980s 500.099us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
clkmgr_shadow_reg_errors 3.980s 500.099us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
clkmgr_shadow_reg_errors 3.980s 500.099us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
clkmgr_shadow_reg_errors_with_csr_rw 7.320s 702.527us 19 20 95.00
sec_cm_bus_integrity 25 25 100.00
clkmgr_tl_intg_err 7.590s 1389.566us 25 25 100.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 13.110s 2389.711us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 22.210s 2415.082us 10 10 100.00
sec_cm_meas_config_shadow 20 20 100.00
clkmgr_shadow_reg_errors 3.980s 500.099us 20 20 100.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 2.200s 297.557us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.420s 108.909us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.480s 111.249us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_clk_handshake_intersig_mubi 1.480s 190.895us 10 10 100.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.490s 102.179us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.400s 141.404us 5 5 100.00
sec_cm_idle_ctr_redun 5 5 100.00
clkmgr_sec_cm 6.040s 1429.682us 5 5 100.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.400s 141.404us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.400s 141.404us 5 5 100.00
prim_count_check 5 5 100.00
clkmgr_sec_cm 6.040s 1429.682us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 6.990s 1009.816us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 67.210s 10540.187us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 47066977229171368947573072821095592976626387889485956195674252592230603654772 82
UVM_INFO @ 133520859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---