Simulation Results: csrng

 
12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.26 %
  • code
  • 96.19 %
  • assert
  • 97.16 %
  • func
  • 92.43 %
  • block
  • 98.50 %
  • line
  • 99.54 %
  • branch
  • 96.32 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.84%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 5.000s 151.040us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 19.948us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 3.000s 17.684us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 18.000s 619.022us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 23.573us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 6.000s 167.737us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 3.000s 17.684us 5 5 100.00
csrng_csr_aliasing 2.000s 23.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
alerts 500 500 100.00
csrng_alert 61.000s 3681.381us 500 500 100.00
err 500 500 100.00
csrng_err 8.000s 34.549us 500 500 100.00
cmds 25 25 100.00
csrng_cmds 329.000s 23517.273us 25 25 100.00
life cycle 25 25 100.00
csrng_cmds 329.000s 23517.273us 25 25 100.00
stress_all 25 25 100.00
csrng_stress_all 1608.000s 82514.774us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 3.000s 58.861us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 4.000s 39.005us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 15.000s 564.046us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 15.000s 564.046us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 2.000s 19.948us 1 1 100.00
csrng_csr_rw 3.000s 17.684us 5 5 100.00
csrng_csr_aliasing 2.000s 23.573us 1 1 100.00
csrng_same_csr_outstanding 8.000s 398.719us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 2.000s 19.948us 1 1 100.00
csrng_csr_rw 3.000s 17.684us 5 5 100.00
csrng_csr_aliasing 2.000s 23.573us 1 1 100.00
csrng_same_csr_outstanding 8.000s 398.719us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 28 30 93.33
csrng_sec_cm 7.000s 343.923us 5 5 100.00
csrng_tl_intg_err 20.000s 457.632us 23 25 92.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 3.000s 14.182us 25 25 100.00
csrng_csr_rw 3.000s 17.684us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 61.000s 3681.381us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 1608.000s 82514.774us 25 25 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
csrng_sec_cm 7.000s 343.923us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
csrng_sec_cm 7.000s 343.923us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
csrng_sec_cm 7.000s 343.923us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
csrng_sec_cm 7.000s 343.923us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
csrng_sec_cm 7.000s 343.923us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 61.000s 3681.381us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 1608.000s 82514.774us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 61.000s 3681.381us 500 500 100.00
sec_cm_tile_link_bus_integrity 23 25 92.00
csrng_tl_intg_err 20.000s 457.632us 23 25 92.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
csrng_sec_cm 7.000s 343.923us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
csrng_sec_cm 7.000s 343.923us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 22.000s 1127.940us 200 200 100.00
csrng_err 8.000s 34.549us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 112.000s 5109.600us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 9 test runs
csrng_stress_all_with_rand_reset 88191709496751055216199789036276449031739123454278847769305393962272217899667 119
UVM_INFO @ 284254925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 79720696835262343166906674243510896397349178055868874690532699299118563475166 178
UVM_INFO @ 5109599765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 111870975137243789704505129130912679165135402677710430212255203195668222659959 110
UVM_INFO @ 13215620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 109865387539328592940929746374845821545195865130585997386620403203919473868314 156
UVM_INFO @ 1698223980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 31582055502189277767629523905182984836542993193622274791863385557537485975260 130
UVM_INFO @ 903345951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 99423250907239271045744025351922093741429247094455840012409770444248749952968 107
UVM_INFO @ 8734724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 92624051019818568120720311839596818295409662190685950658023150679514676883899 194
UVM_INFO @ 2411492516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 11433008054400332692001078553687246478050247402643057655453583524025719864125 177
UVM_INFO @ 1527270438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 62193368133546161429215728989968257058162383892728707778227996812896245809439 117
UVM_INFO @ 41872963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [csrng_common_vseq] Expected alert (fatal_alert) did not fire in * cycles. 2 test runs
csrng_tl_intg_err 93404799242777869929095243210331816480862658681169858612040748569494751736963 163
UVM_INFO @ 233806329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_tl_intg_err 96914181974271550435855986254232981307594316000627143232562027497006267034530 125
UVM_INFO @ 98097153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:180) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 15676365607093109227935983151522881372591034302614703108772534521091060648993 164
UVM_INFO @ 4438882714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---