Simulation Results: edn/edn0

 
12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.74 %
  • code
  • 95.68 %
  • assert
  • 98.48 %
  • func
  • 93.06 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.91 %
  • toggle
  • 97.12 %
  • FSM
  • 91.94 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.57%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.360s 21.368us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.150s 47.003us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.300s 24.475us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 6.110s 2677.768us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.510s 18.959us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.950s 97.568us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.300s 24.475us 5 5 100.00
edn_csr_aliasing 1.510s 18.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 6.060s 373.276us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 6.060s 373.276us 100 100 100.00
genbits 100 100 100.00
edn_genbits 6.060s 373.276us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.600s 21.305us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.870s 189.298us 200 200 100.00
errs 100 100 100.00
edn_err 1.810s 60.466us 100 100 100.00
disable 100 100 100.00
edn_disable 1.320s 16.705us 50 50 100.00
edn_disable_auto_req_mode 2.080s 59.184us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 7.750s 485.030us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.320s 30.491us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.400s 21.317us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.540s 265.611us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.540s 265.611us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.150s 47.003us 1 1 100.00
edn_csr_rw 1.300s 24.475us 5 5 100.00
edn_csr_aliasing 1.510s 18.959us 1 1 100.00
edn_same_csr_outstanding 1.540s 27.292us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.150s 47.003us 1 1 100.00
edn_csr_rw 1.300s 24.475us 5 5 100.00
edn_csr_aliasing 1.510s 18.959us 1 1 100.00
edn_same_csr_outstanding 1.540s 27.292us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
edn_sec_cm 11.830s 2030.069us 5 5 100.00
edn_tl_intg_err 4.080s 645.927us 24 25 96.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.380s 19.407us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.870s 189.298us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.830s 2030.069us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.830s 2030.069us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 11.830s 2030.069us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 11.830s 2030.069us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.870s 189.298us 200 200 100.00
edn_sec_cm 11.830s 2030.069us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.870s 189.298us 200 200 100.00
sec_cm_tile_link_bus_integrity 24 25 96.00
edn_tl_intg_err 4.080s 645.927us 24 25 96.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 30 100.00
edn_stress_all_with_rand_reset 122.620s 25759.294us 30 30 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [edn_common_vseq] Expected alert (fatal_alert) did not fire in * cycles. 1 test run
edn_tl_intg_err 11595421898894020984732393403188770687160345547055497167086402745293658350705 119
UVM_INFO @ 251843567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---