Simulation Results: edn/edn1

 
12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.50 %
  • code
  • 96.10 %
  • assert
  • 98.18 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.69 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
96.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.200s 39.994us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.990s 40.407us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.110s 14.103us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.290s 144.755us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.310s 17.176us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.580s 119.541us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.110s 14.103us 5 5 100.00
edn_csr_aliasing 1.310s 17.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 3.870s 278.326us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 3.870s 278.326us 100 100 100.00
genbits 100 100 100.00
edn_genbits 3.870s 278.326us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.440s 23.549us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.700s 238.397us 200 200 100.00
errs 100 100 100.00
edn_err 1.610s 28.103us 100 100 100.00
disable 100 100 100.00
edn_disable 1.210s 14.173us 50 50 100.00
edn_disable_auto_req_mode 1.640s 368.554us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 6.180s 395.197us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.200s 41.042us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.330s 25.236us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.840s 255.945us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.840s 255.945us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.990s 40.407us 1 1 100.00
edn_csr_rw 1.110s 14.103us 5 5 100.00
edn_csr_aliasing 1.310s 17.176us 1 1 100.00
edn_same_csr_outstanding 1.780s 110.108us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.990s 40.407us 1 1 100.00
edn_csr_rw 1.110s 14.103us 5 5 100.00
edn_csr_aliasing 1.310s 17.176us 1 1 100.00
edn_same_csr_outstanding 1.780s 110.108us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 3.760s 358.200us 5 5 100.00
edn_tl_intg_err 8.680s 2931.318us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.290s 21.156us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.700s 238.397us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.760s 358.200us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.760s 358.200us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 3.760s 358.200us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 3.760s 358.200us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.700s 238.397us 200 200 100.00
edn_sec_cm 3.760s 358.200us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.700s 238.397us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 8.680s 2931.318us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 30 96.67
edn_stress_all_with_rand_reset 133.150s 16474.493us 29 30 96.67

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 79514889730141737531020417889513181482287584208514824866495182287729590028765 294
UVM_INFO @ 16474492845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---