| V1 |
|
100.00% |
| V2 |
|
93.63% |
| V2S |
|
100.00% |
| V3 |
|
35.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 40 | 40 | 100.00 | |||
| gpio_smoke | 1.660s | 200.523us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.850s | 386.305us | 10 | 10 | 100.00 | |
| gpio_smoke_en_cdc_prim | 2.140s | 404.281us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.890s | 185.849us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.830s | 22.955us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| gpio_csr_rw | 0.920s | 17.491us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 2.440s | 163.076us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 0.960s | 38.809us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.300s | 129.030us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| gpio_csr_rw | 0.920s | 17.491us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 0.960s | 38.809us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 20 | 20 | 100.00 | |||
| gpio_random_dout_din | 1.610s | 78.711us | 10 | 10 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.580s | 70.557us | 10 | 10 | 100.00 | |
| out_in_regs_read_write | 10 | 10 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.190s | 61.406us | 10 | 10 | 100.00 | |
| gpio_interrupt_programming | 10 | 10 | 100.00 | |||
| gpio_intr_rand_pgm | 1.820s | 123.248us | 10 | 10 | 100.00 | |
| random_interrupt_trigger | 10 | 10 | 100.00 | |||
| gpio_rand_intr_trigger | 3.540s | 772.328us | 10 | 10 | 100.00 | |
| interrupt_and_noise_filter | 10 | 10 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 3.990s | 181.432us | 10 | 10 | 100.00 | |
| noise_filter_stress | 10 | 10 | 100.00 | |||
| gpio_filter_stress | 28.630s | 583.004us | 10 | 10 | 100.00 | |
| regs_long_reads_and_writes | 10 | 10 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 7.470s | 2929.471us | 10 | 10 | 100.00 | |
| full_random | 10 | 10 | 100.00 | |||
| gpio_full_random | 1.320s | 87.039us | 10 | 10 | 100.00 | |
| stress_all | 0 | 10 | 0.00 | |||
| gpio_stress_all | 42.860s | 6684.986us | 0 | 10 | 0.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| gpio_alert_test | 0.860s | 11.521us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| gpio_intr_test | 0.900s | 17.686us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 2.700s | 56.151us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 2.700s | 56.151us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| gpio_csr_rw | 0.920s | 17.491us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.110s | 123.376us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 0.960s | 38.809us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.830s | 22.955us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| gpio_csr_rw | 0.920s | 17.491us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.110s | 123.376us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 0.960s | 38.809us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.830s | 22.955us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| gpio_tl_intg_err | 1.750s | 130.758us | 25 | 25 | 100.00 | |
| gpio_sec_cm | 1.310s | 94.957us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| gpio_tl_intg_err | 1.750s | 130.758us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 7 | 10 | 70.00 | |||
| gpio_rand_straps | 0.890s | 13.950us | 7 | 10 | 70.00 | |
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 12.670s | 3377.860us | 0 | 10 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:211) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 13 test runs | |||
| gpio_stress_all | 15530263529665082121017586322293797329220573514150700391314514740667948867764 | 198 |
UVM_INFO @ 472049521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 66698561599060906552063965114480817881575413607167134843982021996254786871221 | 84 |
UVM_INFO @ 1602171553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 72027108914141425243294239688162370217469762528233554647078029423836957887020 | 843 |
UVM_INFO @ 6184080119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 74165961510639373755116623170356444716233769995787300966434436592177172708219 | 82 |
UVM_INFO @ 9506695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 22017984780295928822023329606743595415447967568851101428222542079003419406460 | 81 |
UVM_INFO @ 3829838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 14008439580759688341492840519831599293239271033179089041043918238107959088683 | 507 |
UVM_INFO @ 12971358312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 1879132470251505790053727366217873824200763835930368543073315938808461970654 | 81 |
UVM_INFO @ 1212598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 73583646571168922590889654764754477482548546936513496589246656209161964957867 | 1271 |
UVM_INFO @ 6684985983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 32166100073510583992134981619402432313347077967497698489376842820344940549209 | 222 |
UVM_INFO @ 1447776017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 73297385323360809936891674496404633138391664639786046410145881930743858900875 | 543 |
UVM_INFO @ 4876939831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 48122862969426934175623604178619424122018695615974181531363817238628688899073 | 773 |
UVM_INFO @ 3017769815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 86347617926177427742088127977756097380701745507586592852987559500491288451174 | 81 |
UVM_INFO @ 5802273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 38923780468162725808630132952965791165948766173162564377941967604464306401439 | 252 |
UVM_INFO @ 5069119006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 6 test runs | |||
| gpio_stress_all_with_rand_reset | 106216372277659965047918400430117018014609767588094678513642472947304283472209 | 339 |
UVM_INFO @ 3377860432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 112279854803806502267188727075251169024729771354450116576027922510905244684767 | 84 |
UVM_INFO @ 2205067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 12626110840373621011747432414084022922534762158170829513657352769937075093583 | 84 |
UVM_INFO @ 10054454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 40781259102190166660580061245337645735115080900055150648329129975195836470047 | 84 |
UVM_INFO @ 3808575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 4997174190520462424019423504970185045721695041116110279914877077268708389676 | 369 |
UVM_INFO @ 734155478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 113090740358149131450279760264063764618255316803324265772084908281832430049054 | 87 |
UVM_INFO @ 2118694825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1230) [gpio_common_vseq] Check failed (vseq_done) | 4 test runs | |||
| gpio_stress_all_with_rand_reset | 106654342129510178508994177594374031370594727460123176351030314597890128496724 | 86 |
UVM_INFO @ 8309287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 114732228405080850765907243289821755693240958715790621854365559744769887077133 | 227 |
UVM_INFO @ 206397065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 38084924187247847850961850289541579933313482326668597949794564196097455467115 | 86 |
UVM_INFO @ 22554859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 111313766473489273162199205864462514583200309432645393559606136714629370119611 | 88 |
UVM_INFO @ 2254595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|