Simulation Results: hmac

 
12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.94 %
  • code
  • 87.70 %
  • assert
  • 97.60 %
  • func
  • 99.52 %
  • line
  • 99.64 %
  • branch
  • 99.35 %
  • cond
  • 96.30 %
  • toggle
  • 46.17 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 17.730s 6597.932us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.930s 42.836us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.190s 65.887us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 16.720s 3389.534us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.410s 59.254us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 1108.350s 466638.804us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.190s 65.887us 5 5 100.00
hmac_csr_aliasing 1.410s 59.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 121.350s 14613.103us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 143.980s 8341.183us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 272.050s 9518.181us 30 30 100.00
hmac_test_sha384_vectors 611.260s 218830.984us 75 75 100.00
hmac_test_sha512_vectors 595.860s 76314.782us 75 75 100.00
hmac_test_hmac256_vectors 14.520s 870.821us 50 50 100.00
hmac_test_hmac384_vectors 17.130s 490.670us 60 60 100.00
hmac_test_hmac512_vectors 18.880s 988.071us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 32.660s 10342.894us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1835.860s 53922.347us 10 10 100.00
error 10 10 100.00
hmac_error 152.880s 17237.175us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 152.560s 43575.944us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 17.730s 6597.932us 10 10 100.00
hmac_long_msg 121.350s 14613.103us 10 10 100.00
hmac_back_pressure 143.980s 8341.183us 25 25 100.00
hmac_datapath_stress 1835.860s 53922.347us 10 10 100.00
hmac_burst_wr 32.660s 10342.894us 50 50 100.00
hmac_stress_all 4533.680s 144474.117us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 17.730s 6597.932us 10 10 100.00
hmac_long_msg 121.350s 14613.103us 10 10 100.00
hmac_back_pressure 143.980s 8341.183us 25 25 100.00
hmac_datapath_stress 1835.860s 53922.347us 10 10 100.00
hmac_wipe_secret 152.560s 43575.944us 10 10 100.00
hmac_test_sha256_vectors 272.050s 9518.181us 30 30 100.00
hmac_test_sha384_vectors 611.260s 218830.984us 75 75 100.00
hmac_test_sha512_vectors 595.860s 76314.782us 75 75 100.00
hmac_test_hmac256_vectors 14.520s 870.821us 50 50 100.00
hmac_test_hmac384_vectors 17.130s 490.670us 60 60 100.00
hmac_test_hmac512_vectors 18.880s 988.071us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 17.730s 6597.932us 10 10 100.00
hmac_long_msg 121.350s 14613.103us 10 10 100.00
hmac_back_pressure 143.980s 8341.183us 25 25 100.00
hmac_datapath_stress 1835.860s 53922.347us 10 10 100.00
hmac_burst_wr 32.660s 10342.894us 50 50 100.00
hmac_error 152.880s 17237.175us 10 10 100.00
hmac_wipe_secret 152.560s 43575.944us 10 10 100.00
hmac_test_sha256_vectors 272.050s 9518.181us 30 30 100.00
hmac_test_sha384_vectors 611.260s 218830.984us 75 75 100.00
hmac_test_sha512_vectors 595.860s 76314.782us 75 75 100.00
hmac_test_hmac256_vectors 14.520s 870.821us 50 50 100.00
hmac_test_hmac384_vectors 17.130s 490.670us 60 60 100.00
hmac_test_hmac512_vectors 18.880s 988.071us 75 75 100.00
hmac_stress_all 4533.680s 144474.117us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 4533.680s 144474.117us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.900s 17.309us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.950s 20.921us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.280s 730.902us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.280s 730.902us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 0.930s 42.836us 1 1 100.00
hmac_csr_rw 1.190s 65.887us 5 5 100.00
hmac_csr_aliasing 1.410s 59.254us 1 1 100.00
hmac_same_csr_outstanding 2.820s 1025.965us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 0.930s 42.836us 1 1 100.00
hmac_csr_rw 1.190s 65.887us 5 5 100.00
hmac_csr_aliasing 1.410s 59.254us 1 1 100.00
hmac_same_csr_outstanding 2.820s 1025.965us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.300s 487.797us 5 5 100.00
hmac_tl_intg_err 4.690s 275.470us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 4.690s 275.470us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 17.730s 6597.932us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.390s 128.839us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 797.970s 87343.374us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.770s 95.411us 1 1 100.00