Simulation Results

Simulation Results: lc_ctrl/volatile_unlock_disabled

12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
92.20 %

code
85.84 %

assert
94.69 %

func
96.06 %

line
97.28 %

branch
93.90 %

cond
81.49 %

toggle
88.33 %

FSM
68.22 %

Validation stages

V1		100.00%
V2		93.68%
V2S		97.33%
V3		30.00%

33/33 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				20	20	100.00
	lc_ctrl_smoke	4.400s	636.606us	20	20	100.00
csr_hw_reset				1	1	100.00
	lc_ctrl_csr_hw_reset	1.220s	20.849us	1	1	100.00
csr_rw				5	5	100.00
	lc_ctrl_csr_rw	1.280s	32.436us	5	5	100.00
csr_bit_bash				1	1	100.00
	lc_ctrl_csr_bit_bash	2.300s	102.742us	1	1	100.00
csr_aliasing				1	1	100.00
	lc_ctrl_csr_aliasing	1.290s	16.660us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	lc_ctrl_csr_mem_rw_with_rand_reset	1.580s	78.128us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	lc_ctrl_csr_rw	1.280s	32.436us	5	5	100.00
	lc_ctrl_csr_aliasing	1.290s	16.660us	1	1	100.00

400/427 passed

93.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
state_post_trans				20	20	100.00
	lc_ctrl_state_post_trans	8.480s	519.267us	20	20	100.00
regwen_during_op				10	10	100.00
	lc_ctrl_regwen_during_op	11.660s	272.665us	10	10	100.00
rand_wr_claim_transition_if				10	10	100.00
	lc_ctrl_claim_transition_if	1.180s	14.554us	10	10	100.00
lc_prog_failure				20	20	100.00
	lc_ctrl_prog_failure	4.160s	548.899us	20	20	100.00
lc_state_failure				20	20	100.00
	lc_ctrl_state_failure	12.300s	2774.134us	20	20	100.00
lc_errors				18	20	90.00
	lc_ctrl_errors	9.760s	1571.430us	18	20	90.00
security_escalation				121	140	86.43
	lc_ctrl_state_failure	12.300s	2774.134us	20	20	100.00
	lc_ctrl_prog_failure	4.160s	548.899us	20	20	100.00
	lc_ctrl_errors	9.760s	1571.430us	18	20	90.00
	lc_ctrl_security_escalation	10.250s	1513.055us	20	20	100.00
	lc_ctrl_jtag_state_failure	40.850s	6512.489us	12	20	60.00
	lc_ctrl_jtag_prog_failure	10.030s	547.396us	14	20	70.00
	lc_ctrl_jtag_errors	65.050s	19268.201us	17	20	85.00
jtag_access				197	210	93.81
	lc_ctrl_jtag_smoke	12.560s	912.610us	20	20	100.00
	lc_ctrl_jtag_state_post_trans	20.820s	1974.228us	16	20	80.00
	lc_ctrl_jtag_prog_failure	10.030s	547.396us	14	20	70.00
	lc_ctrl_jtag_errors	65.050s	19268.201us	17	20	85.00
	lc_ctrl_jtag_access	13.810s	1128.561us	50	50	100.00
	lc_ctrl_jtag_regwen_during_op	20.620s	3274.723us	10	10	100.00
	lc_ctrl_jtag_csr_hw_reset	3.600s	954.341us	10	10	100.00
	lc_ctrl_jtag_csr_rw	2.310s	421.185us	10	10	100.00
	lc_ctrl_jtag_csr_bit_bash	22.790s	14761.149us	10	10	100.00
	lc_ctrl_jtag_csr_aliasing	3.330s	623.576us	10	10	100.00
	lc_ctrl_jtag_same_csr_outstanding	1.610s	73.370us	10	10	100.00
	lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.400s	293.578us	10	10	100.00
	lc_ctrl_jtag_alert_test	1.690s	55.435us	10	10	100.00
jtag_priority				10	10	100.00
	lc_ctrl_jtag_priority	19.690s	5966.512us	10	10	100.00
lc_ctrl_volatile_unlock				10	10	100.00
	lc_ctrl_volatile_unlock_smoke	1.400s	18.087us	10	10	100.00
stress_all				6	10	60.00
	lc_ctrl_stress_all	386.330s	33995.918us	6	10	60.00
alert_test				10	10	100.00
	lc_ctrl_alert_test	1.300s	78.146us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	lc_ctrl_tl_errors	4.340s	175.530us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	lc_ctrl_tl_errors	4.340s	175.530us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	lc_ctrl_csr_hw_reset	1.220s	20.849us	1	1	100.00
	lc_ctrl_csr_rw	1.280s	32.436us	5	5	100.00
	lc_ctrl_csr_aliasing	1.290s	16.660us	1	1	100.00
	lc_ctrl_same_csr_outstanding	1.810s	106.511us	5	5	100.00
tl_d_partial_access				12	12	100.00
	lc_ctrl_csr_hw_reset	1.220s	20.849us	1	1	100.00
	lc_ctrl_csr_rw	1.280s	32.436us	5	5	100.00
	lc_ctrl_csr_aliasing	1.290s	16.660us	1	1	100.00
	lc_ctrl_same_csr_outstanding	1.810s	106.511us	5	5	100.00

V2S

146/150 passed

97.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	lc_ctrl_sec_cm	10.120s	909.362us	5	5	100.00
	lc_ctrl_tl_intg_err	4.940s	1210.079us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	lc_ctrl_tl_intg_err	4.940s	1210.079us	25	25	100.00
sec_cm_transition_config_regwen				10	10	100.00
	lc_ctrl_regwen_during_op	11.660s	272.665us	10	10	100.00
sec_cm_manuf_state_sparse				25	25	100.00
	lc_ctrl_state_failure	12.300s	2774.134us	20	20	100.00
	lc_ctrl_sec_cm	10.120s	909.362us	5	5	100.00
sec_cm_transition_ctr_sparse				25	25	100.00
	lc_ctrl_state_failure	12.300s	2774.134us	20	20	100.00
	lc_ctrl_sec_cm	10.120s	909.362us	5	5	100.00
sec_cm_manuf_state_bkgn_chk				25	25	100.00
	lc_ctrl_state_failure	12.300s	2774.134us	20	20	100.00
	lc_ctrl_sec_cm	10.120s	909.362us	5	5	100.00
sec_cm_transition_ctr_bkgn_chk				25	25	100.00
	lc_ctrl_state_failure	12.300s	2774.134us	20	20	100.00
	lc_ctrl_sec_cm	10.120s	909.362us	5	5	100.00
sec_cm_state_config_sparse				25	25	100.00
	lc_ctrl_state_failure	12.300s	2774.134us	20	20	100.00
	lc_ctrl_sec_cm	10.120s	909.362us	5	5	100.00
sec_cm_main_fsm_sparse				25	25	100.00
	lc_ctrl_state_failure	12.300s	2774.134us	20	20	100.00
	lc_ctrl_sec_cm	10.120s	909.362us	5	5	100.00
sec_cm_kmac_fsm_sparse				25	25	100.00
	lc_ctrl_state_failure	12.300s	2774.134us	20	20	100.00
	lc_ctrl_sec_cm	10.120s	909.362us	5	5	100.00
sec_cm_main_fsm_local_esc				25	25	100.00
	lc_ctrl_state_failure	12.300s	2774.134us	20	20	100.00
	lc_ctrl_sec_cm	10.120s	909.362us	5	5	100.00
sec_cm_main_fsm_global_esc				20	20	100.00
	lc_ctrl_security_escalation	10.250s	1513.055us	20	20	100.00
sec_cm_main_ctrl_flow_consistency				36	40	90.00
	lc_ctrl_state_post_trans	8.480s	519.267us	20	20	100.00
	lc_ctrl_jtag_state_post_trans	20.820s	1974.228us	16	20	80.00
sec_cm_intersig_mubi				10	10	100.00
	lc_ctrl_sec_mubi	8.760s	336.014us	10	10	100.00
sec_cm_token_valid_ctrl_mubi				10	10	100.00
	lc_ctrl_sec_mubi	8.760s	336.014us	10	10	100.00
sec_cm_token_digest				10	10	100.00
	lc_ctrl_sec_token_digest	16.940s	928.435us	10	10	100.00
sec_cm_token_mux_ctrl_redun				10	10	100.00
	lc_ctrl_sec_token_mux	8.560s	1899.998us	10	10	100.00
sec_cm_token_valid_mux_redun				10	10	100.00
	lc_ctrl_sec_token_mux	8.560s	1899.998us	10	10	100.00

3/10 passed

30.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				3	10	30.00
	lc_ctrl_stress_all_with_rand_reset	60.070s	3587.139us	3	10	30.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error				17 test runs
	lc_ctrl_stress_all	48261220599708500185560245386446413989127877233259944797146886915476610131024	553	UVM_INFO @ 483914466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	14898934051506053223124615504984971606433252555439734181517785333390201202837	211	UVM_INFO @ 20947104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	47367921032765030759290374393199325062458821516822291751083522842027630809747	302	UVM_INFO @ 276818397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	87346980720403461875310505208525882619658306106397810900078172568497752982391	209	UVM_INFO @ 55305348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	68400122001612534249579470097240608269275202493191775166233539676374360158633	611	UVM_INFO @ 3084527985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	103269941718599529383756974393214779087688339084244943239420202211685893136456	1550	UVM_INFO @ 2350730690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	94051823997597646169415417266391582031407795781986242606078485525717560512357	2797	UVM_INFO @ 7112725606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	113706673843450482773872713951474101149715711890804242480050797926145345762816	587	UVM_INFO @ 584361100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	9517401288968695355282550636930377036348460568804559571305498693048405025707	347	UVM_INFO @ 155410929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	102319628217361638783039018328290364515045730060247863071467293618960166444493	255	UVM_INFO @ 241412722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all	98991999903778737529313801201940893033255243868611669905531686023287068838817	714	UVM_INFO @ 4906690755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	16766537142930052606199050432062351676726446758404478781541609659830123861258	1687	UVM_INFO @ 2440339615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	3051405321440667906763048467491709955020223270056976103106804421198562393952	633	UVM_INFO @ 3143657860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	3881963252091367799558344211491676347561407078019256538794580045910563831210	484	UVM_INFO @ 275143337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	39221964475080622602627077229668702931151524206503377629359629316490608932642	805	UVM_INFO @ 6062186707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	91684618604171179821085675263424373028309747658104607917274313979784618338083	628	UVM_INFO @ 1093564353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	104280138192437539585495390387191589916873848483512369059334867849535570486539	3543	UVM_INFO @ 5627021193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error				11 test runs
	lc_ctrl_jtag_prog_failure	30103767115145360092333630077650670226211754720886697266183659251226798682349	336	UVM_INFO @ 241955440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all	80742985746493466108250263626507723763540199477575498259510545997334686813054	507	UVM_INFO @ 2428782802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	65443854477018681371519158541521367570514498989013925170087309669857365071828	337	UVM_INFO @ 1041270421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	102859796618826653238788337872598273892293816802164437858405793761110047363107	207	UVM_INFO @ 324665021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_errors	81411902916630755481698263800838936723778143080891996467851510162499553154227	1674	UVM_INFO @ 1393374981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	113238031284798044299260828824489219176823788859180579096685708417350792878398	250	UVM_INFO @ 318761586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	27572373301012603831807397605266098397604786028401808745566224885561387436291	6917	UVM_INFO @ 1456578037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_errors	112754774339964312363932064831516219909081790555139963941800084839725733547550	2837	UVM_INFO @ 17056338355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	39703054793567913621862691025999872628575077524831632039183933742225297858795	208	UVM_INFO @ 428962199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	42644172258903763837084587521818133002102222340118397708640995493288420451510	333	UVM_INFO @ 548667080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_errors	39756280939799087269490125454729091859389022095851019326393638345209355623138	1165	UVM_INFO @ 2747991987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [] vs [*])				4 test runs
	lc_ctrl_errors	35058678469484212335862834614304641507885036685415265454910951800253526196417	1529	UVM_INFO @ 260961436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all	89950642263216522496725404234470883508821944056282501929547619777746952799977	5123	UVM_INFO @ 26017664970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	2339103131168648975222355757606559096491105765268540898615560393072169891262	3647	UVM_INFO @ 307030206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_errors	71231359169131797843163803271916039401234507776464523320887627840031717039296	1326	UVM_INFO @ 440633852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	lc_ctrl_stress_all_with_rand_reset	59911048602117488897730814227080308231843588895614866020185910318807142750080	319	UVM_INFO @ 812843021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	37142353591057318535157037859850174224270374414802573744568024492994817773991	261	UVM_INFO @ 2697727748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---