Simulation Results

Simulation Results: lc_ctrl/volatile_unlock_enabled

12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
92.41 %

code
86.20 %

assert
94.97 %

func
96.06 %

line
97.26 %

branch
94.29 %

cond
81.97 %

toggle
88.33 %

FSM
69.16 %

Validation stages

V1		100.00%
V2		94.61%
V2S		96.67%
V3		10.00%

33/33 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				20	20	100.00
	lc_ctrl_smoke	4.440s	291.110us	20	20	100.00
csr_hw_reset				1	1	100.00
	lc_ctrl_csr_hw_reset	1.190s	53.960us	1	1	100.00
csr_rw				5	5	100.00
	lc_ctrl_csr_rw	1.250s	14.462us	5	5	100.00
csr_bit_bash				1	1	100.00
	lc_ctrl_csr_bit_bash	1.570s	136.653us	1	1	100.00
csr_aliasing				1	1	100.00
	lc_ctrl_csr_aliasing	1.250s	48.911us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	lc_ctrl_csr_mem_rw_with_rand_reset	1.580s	37.367us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	lc_ctrl_csr_rw	1.250s	14.462us	5	5	100.00
	lc_ctrl_csr_aliasing	1.250s	48.911us	1	1	100.00

404/427 passed

94.61 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
state_post_trans				20	20	100.00
	lc_ctrl_state_post_trans	9.510s	170.857us	20	20	100.00
regwen_during_op				10	10	100.00
	lc_ctrl_regwen_during_op	12.100s	379.364us	10	10	100.00
rand_wr_claim_transition_if				10	10	100.00
	lc_ctrl_claim_transition_if	1.160s	11.429us	10	10	100.00
lc_prog_failure				20	20	100.00
	lc_ctrl_prog_failure	3.650s	141.832us	20	20	100.00
lc_state_failure				20	20	100.00
	lc_ctrl_state_failure	12.380s	390.858us	20	20	100.00
lc_errors				19	20	95.00
	lc_ctrl_errors	8.560s	898.670us	19	20	95.00
security_escalation				127	140	90.71
	lc_ctrl_state_failure	12.380s	390.858us	20	20	100.00
	lc_ctrl_prog_failure	3.650s	141.832us	20	20	100.00
	lc_ctrl_errors	8.560s	898.670us	19	20	95.00
	lc_ctrl_security_escalation	8.170s	519.830us	20	20	100.00
	lc_ctrl_jtag_state_failure	42.050s	2291.724us	15	20	75.00
	lc_ctrl_jtag_prog_failure	17.570s	906.163us	17	20	85.00
	lc_ctrl_jtag_errors	59.100s	4470.681us	16	20	80.00
jtag_access				198	210	94.29
	lc_ctrl_jtag_smoke	10.050s	2781.681us	20	20	100.00
	lc_ctrl_jtag_state_post_trans	19.260s	1214.456us	15	20	75.00
	lc_ctrl_jtag_prog_failure	17.570s	906.163us	17	20	85.00
	lc_ctrl_jtag_errors	59.100s	4470.681us	16	20	80.00
	lc_ctrl_jtag_access	12.390s	1089.722us	50	50	100.00
	lc_ctrl_jtag_regwen_during_op	22.520s	22445.621us	10	10	100.00
	lc_ctrl_jtag_csr_hw_reset	3.350s	884.349us	10	10	100.00
	lc_ctrl_jtag_csr_rw	1.920s	138.752us	10	10	100.00
	lc_ctrl_jtag_csr_bit_bash	13.850s	5156.165us	10	10	100.00
	lc_ctrl_jtag_csr_aliasing	2.950s	488.918us	10	10	100.00
	lc_ctrl_jtag_same_csr_outstanding	1.810s	41.805us	10	10	100.00
	lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.950s	119.470us	10	10	100.00
	lc_ctrl_jtag_alert_test	2.280s	121.916us	10	10	100.00
jtag_priority				8	10	80.00
	lc_ctrl_jtag_priority	35.680s	17886.357us	8	10	80.00
lc_ctrl_volatile_unlock				10	10	100.00
	lc_ctrl_volatile_unlock_smoke	1.390s	29.697us	10	10	100.00
stress_all				7	10	70.00
	lc_ctrl_stress_all	174.410s	45170.836us	7	10	70.00
alert_test				10	10	100.00
	lc_ctrl_alert_test	1.350s	24.577us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	lc_ctrl_tl_errors	5.160s	731.607us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	lc_ctrl_tl_errors	5.160s	731.607us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	lc_ctrl_csr_hw_reset	1.190s	53.960us	1	1	100.00
	lc_ctrl_csr_rw	1.250s	14.462us	5	5	100.00
	lc_ctrl_csr_aliasing	1.250s	48.911us	1	1	100.00
	lc_ctrl_same_csr_outstanding	1.890s	46.366us	5	5	100.00
tl_d_partial_access				12	12	100.00
	lc_ctrl_csr_hw_reset	1.190s	53.960us	1	1	100.00
	lc_ctrl_csr_rw	1.250s	14.462us	5	5	100.00
	lc_ctrl_csr_aliasing	1.250s	48.911us	1	1	100.00
	lc_ctrl_same_csr_outstanding	1.890s	46.366us	5	5	100.00

V2S

145/150 passed

96.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	lc_ctrl_sec_cm	8.470s	251.880us	5	5	100.00
	lc_ctrl_tl_intg_err	3.070s	788.454us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	lc_ctrl_tl_intg_err	3.070s	788.454us	25	25	100.00
sec_cm_transition_config_regwen				10	10	100.00
	lc_ctrl_regwen_during_op	12.100s	379.364us	10	10	100.00
sec_cm_manuf_state_sparse				25	25	100.00
	lc_ctrl_state_failure	12.380s	390.858us	20	20	100.00
	lc_ctrl_sec_cm	8.470s	251.880us	5	5	100.00
sec_cm_transition_ctr_sparse				25	25	100.00
	lc_ctrl_state_failure	12.380s	390.858us	20	20	100.00
	lc_ctrl_sec_cm	8.470s	251.880us	5	5	100.00
sec_cm_manuf_state_bkgn_chk				25	25	100.00
	lc_ctrl_state_failure	12.380s	390.858us	20	20	100.00
	lc_ctrl_sec_cm	8.470s	251.880us	5	5	100.00
sec_cm_transition_ctr_bkgn_chk				25	25	100.00
	lc_ctrl_state_failure	12.380s	390.858us	20	20	100.00
	lc_ctrl_sec_cm	8.470s	251.880us	5	5	100.00
sec_cm_state_config_sparse				25	25	100.00
	lc_ctrl_state_failure	12.380s	390.858us	20	20	100.00
	lc_ctrl_sec_cm	8.470s	251.880us	5	5	100.00
sec_cm_main_fsm_sparse				25	25	100.00
	lc_ctrl_state_failure	12.380s	390.858us	20	20	100.00
	lc_ctrl_sec_cm	8.470s	251.880us	5	5	100.00
sec_cm_kmac_fsm_sparse				25	25	100.00
	lc_ctrl_state_failure	12.380s	390.858us	20	20	100.00
	lc_ctrl_sec_cm	8.470s	251.880us	5	5	100.00
sec_cm_main_fsm_local_esc				25	25	100.00
	lc_ctrl_state_failure	12.380s	390.858us	20	20	100.00
	lc_ctrl_sec_cm	8.470s	251.880us	5	5	100.00
sec_cm_main_fsm_global_esc				20	20	100.00
	lc_ctrl_security_escalation	8.170s	519.830us	20	20	100.00
sec_cm_main_ctrl_flow_consistency				35	40	87.50
	lc_ctrl_state_post_trans	9.510s	170.857us	20	20	100.00
	lc_ctrl_jtag_state_post_trans	19.260s	1214.456us	15	20	75.00
sec_cm_intersig_mubi				10	10	100.00
	lc_ctrl_sec_mubi	13.260s	7122.637us	10	10	100.00
sec_cm_token_valid_ctrl_mubi				10	10	100.00
	lc_ctrl_sec_mubi	13.260s	7122.637us	10	10	100.00
sec_cm_token_digest				10	10	100.00
	lc_ctrl_sec_token_digest	8.960s	2296.227us	10	10	100.00
sec_cm_token_mux_ctrl_redun				10	10	100.00
	lc_ctrl_sec_token_mux	7.940s	423.428us	10	10	100.00
sec_cm_token_valid_mux_redun				10	10	100.00
	lc_ctrl_sec_token_mux	7.940s	423.428us	10	10	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	lc_ctrl_stress_all_with_rand_reset	36.960s	9203.896us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error				17 test runs
	lc_ctrl_jtag_state_post_trans	45103577189355274665007212500088852893922929057824508269212040916293526769565	355	UVM_INFO @ 242756597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	107531456108410777997070617402192157285700022597403557869396827704137963111458	1997	UVM_INFO @ 5950889921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all	68174317246611712261165859429458153041335687733295687799922903453641655067130	3040	UVM_INFO @ 1232437477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	113966229584659193130284017483796907669208791706631877146166367551835310405662	2754	UVM_INFO @ 1755605717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all	5000968005559491398043823626610826083199483338091948725165842627388604334861	6086	UVM_INFO @ 5617935320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	102257295127500891768739436049137342267710805977942180429567599913298180662165	450	UVM_INFO @ 319950289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	92093826694197864180382260973499340558342932212805516036780172850683365759472	4599	UVM_INFO @ 9203896417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	15044322193105504328889401656193258615394059340341146944150974263462783079637	616	UVM_INFO @ 378420296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	55396943969385738616866150527614228836951337951800352336787026109656941353232	5483	UVM_INFO @ 5499145429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	30875002610735785171749360020944455565871591496522674488726836813226918743801	576	UVM_INFO @ 224937276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	5998504686667690455948555829151721466938722094478865448051808679647742589441	4523	UVM_INFO @ 1751963294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all	4939499141724387833214114689740983248587786884977460055220459086294027777347	1093	UVM_INFO @ 998523434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	22357493080987026917641361158925545574411175105218569786890808765786426710209	669	UVM_INFO @ 647713680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	23282595684036987211192290255448299321790354840781555448173205171638744214714	212	UVM_INFO @ 68371718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	70628207578276194457344240969908875976010293709574810160518524753219355128992	390	UVM_INFO @ 791884936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	104225481514176235474985151923277602798736722440835781629488247622352474463552	578	UVM_INFO @ 2787807902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	39510972741457746724636080456507555968923090377966724811330501386227198245183	209	UVM_INFO @ 128756508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error				7 test runs
	lc_ctrl_stress_all_with_rand_reset	96975972929488388917628843524110790726028890253243157302611351164731812987929	1596	UVM_INFO @ 2789669866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	95502752709172943255007318009902825433243269856590591311604148490104486477926	590	UVM_INFO @ 3385634225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	38304140437499877916717807445022226739938841129797954919338869162076305092406	208	UVM_INFO @ 916237276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_errors	47539073348669788095131414678408644158846531759684763450188982514229015947141	1714	UVM_INFO @ 698700184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_errors	76350130651743004713749485677043917022119163427885975531761285376216560823189	1884	UVM_INFO @ 1026118599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	85229615527859231955280214021565753637542154296733667398334342611039614983251	676	UVM_INFO @ 683480136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_errors	99308743077004777306926422348407605100033872544883189907286464131820243895513	2384	UVM_INFO @ 3252150447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				4 test runs
	lc_ctrl_stress_all_with_rand_reset	12108603774574837494594108075055637510281695101272227095061610529117263489578	3290	UVM_INFO @ 1355964287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	19929902826322329763615418981607946489430695765904738498060904590308311776238	2165	UVM_INFO @ 4205309088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	57580531752706228219930747459542114569645060788380353933384064847892361672305	3233	UVM_INFO @ 3966465274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	70433258615487774684317453077077095856814987588754508781102219186716752137797	274	UVM_INFO @ 746777454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [] vs [*])				2 test runs
	lc_ctrl_errors	36354786423464176347715125573539008042209825843940771274546335548534245854971	2273	UVM_INFO @ 267482415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_errors	56838667445171321311757522665041925315547563219273551120835607161603324377172	1424	UVM_INFO @ 24472867951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred!				2 test runs
	lc_ctrl_jtag_priority	45873459861461257258310823058391750718087501542637301111017743636935325496227	166	UVM_INFO @ 10017153663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_priority	77456966878413939872242764017968066908508953545482470467254977596781963508086	166	UVM_INFO @ 10014629642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---