Simulation Results

Simulation Results: otbn

12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.01 %

code
82.58 %

assert
96.45 %

func
100.00 %

block
97.79 %

line
98.00 %

branch
82.17 %

toggle
82.55 %

FSM
67.61 %

Validation stages

V1		99.15%
V2		93.53%
V2S		96.05%
V3		0.00%

116/117 passed

99.15 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	otbn_smoke	15.000s	63.455us	1	1	100.00
	otbn_smoke_vectorized	11.000s	21.124us	1	1	100.00
single_binary				99	100	99.00
	otbn_single	66.000s	145.687us	99	100	99.00
csr_hw_reset				1	1	100.00
	otbn_csr_hw_reset	6.000s	117.772us	1	1	100.00
csr_rw				5	5	100.00
	otbn_csr_rw	6.000s	37.349us	5	5	100.00
csr_bit_bash				1	1	100.00
	otbn_csr_bit_bash	11.000s	144.972us	1	1	100.00
csr_aliasing				1	1	100.00
	otbn_csr_aliasing	5.000s	13.966us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	otbn_csr_mem_rw_with_rand_reset	12.000s	45.734us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otbn_csr_rw	6.000s	37.349us	5	5	100.00
	otbn_csr_aliasing	5.000s	13.966us	1	1	100.00
mem_walk				1	1	100.00
	otbn_mem_walk	176.000s	30914.199us	1	1	100.00
mem_partial_access				1	1	100.00
	otbn_mem_partial_access	74.000s	5519.254us	1	1	100.00

159/170 passed

93.53 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	66.000s	537.513us	10	10	100.00
multi_error				0	1	0.00
	otbn_multi_err	12.000s	62.487us	0	1	0.00
wfi				4	7	57.14
	otbn_wfi_smoke	7.000s	13.756us	0	1	0.00
	otbn_wfi_sec_wipe	25.000s	28.127us	4	5	80.00
	otbn_wfi_back_to_back	6.000s	19.012us	0	1	0.00
back_to_back				10	10	100.00
	otbn_multi	182.000s	1129.056us	10	10	100.00
stress_all				8	10	80.00
	otbn_stress_all	135.000s	2610.940us	8	10	80.00
lc_escalation				56	60	93.33
	otbn_escalate	63.000s	267.248us	56	60	93.33
zero_state_err_urnd				4	5	80.00
	otbn_zero_state_err_urnd	11.000s	46.806us	4	5	80.00
sw_errs_fatal_chk				10	10	100.00
	otbn_sw_errs_fatal_chk	111.000s	1052.710us	10	10	100.00
alert_test				10	10	100.00
	otbn_alert_test	13.000s	21.766us	10	10	100.00
intr_test				10	10	100.00
	otbn_intr_test	6.000s	50.955us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otbn_tl_errors	19.000s	114.669us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otbn_tl_errors	19.000s	114.669us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otbn_csr_hw_reset	6.000s	117.772us	1	1	100.00
	otbn_csr_rw	6.000s	37.349us	5	5	100.00
	otbn_csr_aliasing	5.000s	13.966us	1	1	100.00
	otbn_same_csr_outstanding	12.000s	21.442us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otbn_csr_hw_reset	6.000s	117.772us	1	1	100.00
	otbn_csr_rw	6.000s	37.349us	5	5	100.00
	otbn_csr_aliasing	5.000s	13.966us	1	1	100.00
	otbn_same_csr_outstanding	12.000s	21.442us	5	5	100.00

V2S

316/329 passed

96.05 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				24	25	96.00
	otbn_imem_err	14.000s	22.285us	9	10	90.00
	otbn_dmem_err	18.000s	38.040us	15	15	100.00
internal_integrity				17	17	100.00
	otbn_alu_bignum_mod_err	16.000s	220.880us	5	5	100.00
	otbn_controller_ispr_rdata_err	14.000s	310.999us	5	5	100.00
	otbn_mac_bignum_acc_err	31.000s	233.140us	5	5	100.00
	otbn_urnd_err	9.000s	11.566us	2	2	100.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	11.000s	469.661us	5	5	100.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	9.000s	14.793us	2	2	100.00
otbn_non_sec_partial_wipe				9	10	90.00
	otbn_partial_wipe	10.000s	25.998us	9	10	90.00
tl_intg_err				30	30	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
	otbn_tl_intg_err	48.000s	209.464us	25	25	100.00
passthru_mem_tl_intg_err				3	5	60.00
	otbn_passthru_mem_tl_intg_err	80.000s	246.677us	3	5	60.00
prim_fsm_check				5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
prim_count_check				5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	15.000s	63.455us	1	1	100.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	18.000s	38.040us	15	15	100.00
sec_cm_instruction_mem_integrity				9	10	90.00
	otbn_imem_err	14.000s	22.285us	9	10	90.00
sec_cm_bus_integrity				25	25	100.00
	otbn_tl_intg_err	48.000s	209.464us	25	25	100.00
sec_cm_controller_fsm_global_esc				56	60	93.33
	otbn_escalate	63.000s	267.248us	56	60	93.33
sec_cm_controller_fsm_local_esc				38	40	95.00
	otbn_imem_err	14.000s	22.285us	9	10	90.00
	otbn_dmem_err	18.000s	38.040us	15	15	100.00
	otbn_zero_state_err_urnd	11.000s	46.806us	4	5	80.00
	otbn_illegal_mem_acc	11.000s	469.661us	5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_controller_fsm_sparse				5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_scramble_key_sideload				99	100	99.00
	otbn_single	66.000s	145.687us	99	100	99.00
sec_cm_scramble_ctrl_fsm_local_esc				38	40	95.00
	otbn_imem_err	14.000s	22.285us	9	10	90.00
	otbn_dmem_err	18.000s	38.040us	15	15	100.00
	otbn_zero_state_err_urnd	11.000s	46.806us	4	5	80.00
	otbn_illegal_mem_acc	11.000s	469.661us	5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_scramble_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_global_esc				56	60	93.33
	otbn_escalate	63.000s	267.248us	56	60	93.33
sec_cm_start_stop_ctrl_fsm_local_esc				38	40	95.00
	otbn_imem_err	14.000s	22.285us	9	10	90.00
	otbn_dmem_err	18.000s	38.040us	15	15	100.00
	otbn_zero_state_err_urnd	11.000s	46.806us	4	5	80.00
	otbn_illegal_mem_acc	11.000s	469.661us	5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_data_reg_sw_sca				99	100	99.00
	otbn_single	66.000s	145.687us	99	100	99.00
sec_cm_ctrl_redun				12	12	100.00
	otbn_ctrl_redun	13.000s	39.549us	12	12	100.00
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	13.000s	29.148us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	549.000s	1668.526us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	549.000s	1668.526us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				10	10	100.00
	otbn_rf_base_intg_err	22.000s	545.020us	10	10	100.00
sec_cm_rf_base_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_stack_wr_ptr_ctr_redun				5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_rf_bignum_data_reg_sw_integrity				8	10	80.00
	otbn_rf_bignum_intg_err	20.000s	61.661us	8	10	80.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_loop_stack_ctr_redun				5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00
sec_cm_loop_stack_addr_integrity				4	5	80.00
	otbn_stack_addr_integ_chk	69.000s	176.515us	4	5	80.00
sec_cm_call_stack_addr_integrity				4	5	80.00
	otbn_stack_addr_integ_chk	69.000s	176.515us	4	5	80.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	22.000s	38.411us	7	7	100.00
sec_cm_data_mem_sec_wipe				99	100	99.00
	otbn_single	66.000s	145.687us	99	100	99.00
sec_cm_instruction_mem_sec_wipe				99	100	99.00
	otbn_single	66.000s	145.687us	99	100	99.00
sec_cm_data_reg_sw_sec_wipe				99	100	99.00
	otbn_single	66.000s	145.687us	99	100	99.00
sec_cm_write_mem_integrity				10	10	100.00
	otbn_multi	182.000s	1129.056us	10	10	100.00
sec_cm_ctrl_flow_count				99	100	99.00
	otbn_single	66.000s	145.687us	99	100	99.00
sec_cm_ctrl_flow_sca				99	100	99.00
	otbn_single	66.000s	145.687us	99	100	99.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	30.000s	24.877us	5	5	100.00
sec_cm_key_sideload				99	100	99.00
	otbn_single	66.000s	145.687us	99	100	99.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	otbn_sec_cm	795.000s	10307.602us	5	5	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	otbn_stress_all_with_rand_reset	92.000s	319.800us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -*				9 test runs
	otbn_stress_all_with_rand_reset	45222749586929273330602325538264644201103956768554086727993970872248328476862	153	UVM_INFO @ 26094745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	109966835752150768227536491734410655062261324314462756406819249330360221571717	165	UVM_INFO @ 339951165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	88831015710165352486961964068568341130176129385051660340674321941729250550758	156	UVM_INFO @ 62579030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	19441362646214893656361912458891312964347305523983247082335900541131298400244	151	UVM_INFO @ 33161663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	44092643578060441590784713244925872292932794863969439904383578022814164687449	159	UVM_INFO @ 114183616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	32440049113733760960622801861828272368064844521592802920995040226693699806156	150	UVM_INFO @ 11983869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	69136590263104541766927897797299775917446550450127046133581548336469367329113	153	UVM_INFO @ 294664275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	28468380959814627204515472475104112625045710670381232170686011389887560975617	155	UVM_INFO @ 34875456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	95461793519042024492186670082689925771838722516491522509864333280877901873091	159	UVM_INFO @ 80008892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.				5 test runs
	otbn_multi_err	90200297239154621321960095627134275215913910027032896747960561149583088414600	207	UVM_INFO @ 62487035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all	63479552244221720673253999357009567809382165130307906472882233224910726540528	144	UVM_INFO @ 236301581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_passthru_mem_tl_intg_err	47524401703749243987031587012180473006731329689459991443894644725515445689946	86	UVM_INFO @ 1179338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all	33613665868118613371713852706297215511932738097999107458888908939255081630726	203	UVM_INFO @ 543553127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_single	63538726023206794217780024030713612143943826631555114905243451713263646161041	107	UVM_INFO @ 16705022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed				4 test runs
	otbn_zero_state_err_urnd	64808900042125911376696315290965869636444295665352804861309845145637674433987	111	UVM_ERROR @ 26319116 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 26319116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stack_addr_integ_chk	53831289744446514073195493687392168744222234753577549101005417014642374088291	121	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,158): (time 45467322 PS) Assertion tb.model_if.NoModelErrs has failed UVM_ERROR @ 45467322 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 45467322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	107957272102368326270529247733611045663338828264271568563998023020286601665812	113	UVM_ERROR @ 36064645 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 36064645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	12658928747060009571501534840235095360165309368394133531131265344202181244957	117	UVM_ERROR @ 38527079 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 38527079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				3 test runs
	otbn_partial_wipe	17886901323585023365504664795407431945355799627422117230604982786521807701405	106	UVM_INFO @ 15407640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rf_bignum_intg_err	99733450787519363053383717390202693392074061984675051338744626985656553596977	111	UVM_INFO @ 31447880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	89278556458926780611229863648807730053592046552867611757180966595588975057305	103	UVM_INFO @ 150090130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [] vs [*]) Saw instruction when not in BUSY_EXECUTE operational state.				2 test runs
	otbn_wfi_smoke	37482366824870861748018992492224027184960970121684475080120987029486288832075	119	UVM_INFO @ 13756205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_wfi_back_to_back	16441940705399522000803936896162423882564378421284800428191047541057040496142	114	UVM_INFO @ 19011933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_/otbn_model_if.sv,158): Assertion NoModelErrs has failed				1 test run
	otbn_rf_bignum_intg_err	78268264325673882738130929110327613232465693910508690931778360985752215500043	122	UVM_ERROR @ 12278523 ps: (otbn_model_if.sv:158) [ASSERT FAILED] NoModelErrs UVM_INFO @ 12278523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.				1 test run
	otbn_passthru_mem_tl_intg_err	103559656851802580635193739917488059350166757377944689097110857670873262236392	91	UVM_INFO @ 18868319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_env_cov.sv, Line: ):(Time: PS + ) Sampled value () for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@_.cur_cp) is an illegal value.				1 test run
	otbn_wfi_sec_wipe	88708794040605773563097767653846742408840497326928230807272355457138953612887	111	UVM_FATAL @ 21449264 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi' UVM_INFO @ 21449264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				1 test run
	otbn_imem_err	104403111810454795121790350847309175001359214124514722429606362895947731738612	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	otbn_stress_all_with_rand_reset	92810196764095961752238354161397629430501487728232264286580474715321311183219	157	UVM_INFO @ 319800119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [] vs [*]) value for register otbn_reg_block.status				1 test run
	otbn_escalate	112224351830892241259307280730737388760645430677906876387619465663222552338672	109	UVM_INFO @ 20373368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---