Simulation Results

Simulation Results: otp_ctrl

12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
90.66 %

code
85.41 %

assert
95.47 %

func
91.11 %

line
90.24 %

branch
86.75 %

cond
94.06 %

toggle
92.82 %

FSM
63.19 %

Validation stages

V1		96.15%
V2		74.63%
V2S		75.15%
V3		12.87%

25/26 passed

96.15 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	1.970s	53.477us	1	1	100.00
smoke				10	10	100.00
	otp_ctrl_smoke	19.240s	4770.019us	10	10	100.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	2.380s	92.660us	1	1	100.00
csr_rw				5	5	100.00
	otp_ctrl_csr_rw	2.680s	551.999us	5	5	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	4.130s	105.459us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	3.450s	185.750us	1	1	100.00
csr_mem_rw_with_rand_reset				4	5	80.00
	otp_ctrl_csr_mem_rw_with_rand_reset	3.570s	291.070us	4	5	80.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otp_ctrl_csr_rw	2.680s	551.999us	5	5	100.00
	otp_ctrl_csr_aliasing	3.450s	185.750us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	2.050s	144.190us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	1.500s	145.487us	1	1	100.00

562/753 passed

74.63 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				1	1	100.00
	otp_ctrl_partition_walk	18.980s	935.189us	1	1	100.00
init_fail				245	300	81.67
	otp_ctrl_init_fail	7.950s	2328.476us	245	300	81.67
partition_check				34	60	56.67
	otp_ctrl_background_chks	36.960s	12010.701us	7	10	70.00
	otp_ctrl_check_fail	205.680s	23239.468us	27	50	54.00
regwen_during_otp_init				30	30	100.00
	otp_ctrl_regwen	11.090s	1047.109us	30	30	100.00
partition_lock				30	30	100.00
	otp_ctrl_dai_lock	121.940s	34007.690us	30	30	100.00
interface_key_check				5	10	50.00
	otp_ctrl_parallel_key_req	34.960s	17019.487us	5	10	50.00
lc_interactions				134	210	63.81
	otp_ctrl_parallel_lc_req	30.190s	2980.139us	10	10	100.00
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
otp_dai_errors				10	25	40.00
	otp_ctrl_dai_errs	33.380s	1395.831us	10	25	40.00
otp_macro_errors				3	10	30.00
	otp_ctrl_macro_errs	52.680s	5916.180us	3	10	30.00
test_access				10	10	100.00
	otp_ctrl_test_access	31.070s	15312.846us	10	10	100.00
stress_all				3	10	30.00
	otp_ctrl_stress_all	283.540s	25899.457us	3	10	30.00
intr_test				10	10	100.00
	otp_ctrl_intr_test	2.860s	542.248us	10	10	100.00
alert_test				10	10	100.00
	otp_ctrl_alert_test	4.350s	1006.108us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otp_ctrl_tl_errors	8.290s	1043.817us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otp_ctrl_tl_errors	8.290s	1043.817us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otp_ctrl_csr_hw_reset	2.380s	92.660us	1	1	100.00
	otp_ctrl_csr_rw	2.680s	551.999us	5	5	100.00
	otp_ctrl_csr_aliasing	3.450s	185.750us	1	1	100.00
	otp_ctrl_same_csr_outstanding	4.330s	2169.425us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otp_ctrl_csr_hw_reset	2.380s	92.660us	1	1	100.00
	otp_ctrl_csr_rw	2.680s	551.999us	5	5	100.00
	otp_ctrl_csr_aliasing	3.450s	185.750us	1	1	100.00
	otp_ctrl_same_csr_outstanding	4.330s	2169.425us	5	5	100.00

V2S

496/660 passed

75.15 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
tl_intg_err				27	30	90.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
	otp_ctrl_tl_intg_err	25.240s	3147.622us	23	25	92.00
prim_count_check				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
prim_fsm_check				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_bus_integrity				23	25	92.00
	otp_ctrl_tl_intg_err	25.240s	3147.622us	23	25	92.00
sec_cm_secret_mem_scramble				10	10	100.00
	otp_ctrl_smoke	19.240s	4770.019us	10	10	100.00
sec_cm_part_mem_digest				10	10	100.00
	otp_ctrl_smoke	19.240s	4770.019us	10	10	100.00
sec_cm_dai_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_kdi_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_lci_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_part_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_scrmbl_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_timer_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_dai_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_kdi_seed_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_kdi_entropy_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_lci_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_part_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_scrmbl_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_timer_integ_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_timer_cnsty_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_timer_lfsr_redun				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_dai_fsm_local_esc				128	205	62.44
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_lci_fsm_local_esc				124	200	62.00
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
sec_cm_kdi_fsm_local_esc				124	200	62.00
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
sec_cm_part_fsm_local_esc				127	210	60.48
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
	otp_ctrl_macro_errs	52.680s	5916.180us	3	10	30.00
sec_cm_scrmbl_fsm_local_esc				124	200	62.00
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
sec_cm_timer_fsm_local_esc				128	205	62.44
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_dai_fsm_global_esc				128	205	62.44
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_lci_fsm_global_esc				124	200	62.00
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
sec_cm_kdi_fsm_global_esc				124	200	62.00
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
sec_cm_part_fsm_global_esc				127	210	60.48
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
	otp_ctrl_macro_errs	52.680s	5916.180us	3	10	30.00
sec_cm_scrmbl_fsm_global_esc				124	200	62.00
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
sec_cm_timer_fsm_global_esc				128	205	62.44
	otp_ctrl_parallel_lc_esc	35.840s	19154.962us	124	200	62.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_part_data_reg_integrity				245	300	81.67
	otp_ctrl_init_fail	7.950s	2328.476us	245	300	81.67
sec_cm_part_data_reg_bkgn_chk				27	50	54.00
	otp_ctrl_check_fail	205.680s	23239.468us	27	50	54.00
sec_cm_part_mem_regren				30	30	100.00
	otp_ctrl_dai_lock	121.940s	34007.690us	30	30	100.00
sec_cm_part_mem_sw_unreadable				30	30	100.00
	otp_ctrl_dai_lock	121.940s	34007.690us	30	30	100.00
sec_cm_part_mem_sw_unwritable				30	30	100.00
	otp_ctrl_dai_lock	121.940s	34007.690us	30	30	100.00
sec_cm_lc_part_mem_sw_noaccess				30	30	100.00
	otp_ctrl_dai_lock	121.940s	34007.690us	30	30	100.00
sec_cm_access_ctrl_mubi				30	30	100.00
	otp_ctrl_dai_lock	121.940s	34007.690us	30	30	100.00
sec_cm_token_valid_ctrl_mubi				10	10	100.00
	otp_ctrl_smoke	19.240s	4770.019us	10	10	100.00
sec_cm_lc_ctrl_intersig_mubi				30	30	100.00
	otp_ctrl_dai_lock	121.940s	34007.690us	30	30	100.00
sec_cm_test_bus_lc_gated				10	10	100.00
	otp_ctrl_smoke	19.240s	4770.019us	10	10	100.00
sec_cm_test_tl_lc_gate_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	182.970s	44985.200us	4	5	80.00
sec_cm_direct_access_config_regwen				30	30	100.00
	otp_ctrl_regwen	11.090s	1047.109us	30	30	100.00
sec_cm_check_trigger_config_regwen				10	10	100.00
	otp_ctrl_smoke	19.240s	4770.019us	10	10	100.00
sec_cm_check_config_regwen				10	10	100.00
	otp_ctrl_smoke	19.240s	4770.019us	10	10	100.00
sec_cm_macro_mem_integrity				3	10	30.00
	otp_ctrl_macro_errs	52.680s	5916.180us	3	10	30.00

13/101 passed

12.87 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
otp_ctrl_low_freq_read				1	1	100.00
	otp_ctrl_low_freq_read	26.260s	7981.756us	1	1	100.00
stress_all_with_rand_reset				12	100	12.00
	otp_ctrl_stress_all_with_rand_reset	3600.145s	0.000us	12	100	12.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *)				76 test runs
	otp_ctrl_parallel_lc_esc	79842954214126794429145672980043214485107360314282545126033202374437037817194	2801	UVM_INFO @ 3036223382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	20705223958882370897064471966667097975082525085229917782610104100456659455023	1709	UVM_INFO @ 317508756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	1738125004934318353678238249197689645462625523566577638773583635828160484559	4381	UVM_INFO @ 514221659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	17523852095812189239971150358890291930825492239407902937052180463669207983005	11011	UVM_INFO @ 1309218392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	79996880287182040387872302664379625649231276627974809088987481664751969675789	5035	UVM_INFO @ 140339948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	59581279661744918075687529069862039722337438384457799818619774587111366919853	4241	UVM_INFO @ 656354798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	111330292910823781530391751092548389823005770861154406093708317022793002099259	108567	UVM_INFO @ 63747922990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	60117371483529469547424624352199548965927319773028675001174072524808455333136	1658	UVM_INFO @ 281718413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	26900921712957420425392098870188089074113085943824732147776302405148257894978	8913	UVM_INFO @ 4324572512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	96579944597696235054991535167372781458966717274675682179557829310207684447232	2583	UVM_INFO @ 388695594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	47304781876249778461644083324173792947948892509982121605856272642520449709598	3894	UVM_INFO @ 784079527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	82830973430466280443822061332626259444565598895732428817366747251337759823794	4118	UVM_INFO @ 310315304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	23266829828549259471057955683561675765037567662622097551023427599221747992499	8349	UVM_INFO @ 2074481418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	19773368822669886153125698901373671927665190019341821605178742036749944843181	15359	UVM_INFO @ 42518866863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	51869440726728327032890458977909111195614217535426392855583559349472058682137	2932	UVM_INFO @ 1152507876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	48827009678307735201512422171667146625578447699377900540461278605159979340813	6574	UVM_INFO @ 2165092367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	78637448881837835913988737189571797028502741759361085088985899507880732016130	2861	UVM_INFO @ 791756449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	60835722866809382684857101465401752938710195481219114840652078409168419482932	5480	UVM_INFO @ 442398777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	54136279262841246412767661121608829651089358215738553361458009875662062264666	7509	UVM_INFO @ 3349915763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	81828876271492414707040047643279197348151725231320838199039865126138546392312	5516	UVM_INFO @ 1067234290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	51167390223391870207735849093800161543296584417921367846715382253757286964327	3656	UVM_INFO @ 240743622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	40281225980749617234660635246151471585703140367182789464252004936008287692359	6938	UVM_INFO @ 1037046256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	22044654756564268185568606047979327821210660256556494686171049496122882680689	1039	UVM_INFO @ 1828849350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	48498535080971773026034498174125658289946583328570713796626076899924215856054	2994	UVM_INFO @ 598062264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	96907670115058027120110044328752533934760000897598006480516312825066050990283	7294	UVM_INFO @ 1791024204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	113359524800921488369460614684181269189439833980666086155084400281247442990436	1288	UVM_INFO @ 1575270315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	30673003652836258849777972195815547780554500439891415910546664775118883213812	749	UVM_INFO @ 139439726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	95332777275057606215068134897787888592212428630938294810268392330685964280111	8632	UVM_INFO @ 331860341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	89723122971261869482971749851104603374481606184584822454071680304262763615121	1028	UVM_INFO @ 185398591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	56723829165170916804502725069634741862033327735073953525420305202722039676459	1824	UVM_INFO @ 292691576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	37367842279649032271669659095140504448040902229524777908325426851849118526677	3598	UVM_INFO @ 503043162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	21058595406578875286292399064526024223059767091038079970168315603558124290594	2011	UVM_INFO @ 522603160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	114717257746504503660392105256760552587167146560313778847832702983194512268660	2426	UVM_INFO @ 8751479714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	30478818263499846916834770639371587191165919939112662276319635685801534668066	3543	UVM_INFO @ 722912377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	90667805082546530549565402538696166069235082175968390284363933761545262856851	1572	UVM_INFO @ 112686417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	53011240573076792920054369916431697115461782130069496647159662370615072504632	1484	UVM_INFO @ 133354367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	60219751576158291887342240100349815808977897430432826900805536184399643233843	4877	UVM_INFO @ 2882040165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	29799589001840641937233078059528740011391563251278876440268608370267103786386	3217	UVM_INFO @ 517321471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	53337980969500011827157454774360544250088383317822755253243153981124014080744	7577	UVM_INFO @ 499993375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	77369338621955303255223354386709459778321769598929138053289672622494850373421	6839	UVM_INFO @ 2447005329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	52557601345218376899116185282143863085802169824229930759126801009147964329280	2470	UVM_INFO @ 698678616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	65530857196287778091840393717452746699825757205194777587332111108104031680388	613	UVM_INFO @ 231109073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	60089833561598365729238315261018317653427250938849379448595728678491184939209	982	UVM_INFO @ 94203487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	19992103302793788168592710372208704372587600135451821625615189550520460774873	2101	UVM_INFO @ 2329585250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	89203233294494013253679663211211278364888100817917497505041978978135387459134	1894	UVM_INFO @ 2159201115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	30429889767883995839362567533851915925112108917584493206110703830715566921265	238	UVM_INFO @ 964317041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	63637920630871440866835683906205270730712824226410816957955470442952331858399	1001	UVM_INFO @ 204200245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	114739819791635077654241105916610307033909781760925063580204332265598691547779	16257	UVM_INFO @ 3244284521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	63909984368293499441508351225703400976817522832391737008760492367355663431627	5590	UVM_INFO @ 3276777102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	78018429225773646115222333322020933968944950819252352145035436677714939309475	2882	UVM_INFO @ 3436103881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	54903392316556885816030343564252164604227414236870708855858559619298585007526	6365	UVM_INFO @ 395862720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	85716529156603560013517600767659048790636652490327897149539218231685901921163	1273	UVM_INFO @ 436917369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	83803386505895055371444289064334367282216328989157131872852536259492627831275	655	UVM_INFO @ 595856156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	41046812375630656063511938463709700815463701753320543064883215372378562970920	3525	UVM_INFO @ 234650286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	5442254121808117998809163608553396777885508099168238791947016241042010127109	3144	UVM_INFO @ 545102058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	96572616804292064666413254673970283394569873470297254902093629832383660014292	2753	UVM_INFO @ 2931339856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	58250819098010430118466946293908278535870120343895762138003586036447188467227	2313	UVM_INFO @ 2569958415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	100585073150109511113950116982493539011244281986664628957609286075102699042709	1160	UVM_INFO @ 330411723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	8033802264738493695223327674930241022586393393993617030348904967258700061396	2676	UVM_INFO @ 391174221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	102135802242070012469585408222310064105522729788740783342766559152014302263928	1239	UVM_INFO @ 385775028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	95481337507797875567137579233351625534821839026821265582050829462458378079508	3826	UVM_INFO @ 258273138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	22367565578325178818643875947795065078164137462175352515517704154629890062453	639	UVM_INFO @ 1203977224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	49190115337086044623789491976182967841046168931742601404183670154564323599308	7259	UVM_INFO @ 528271413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	96612457270158889283013042899464946866174009505658680901349539356182663249324	7255	UVM_INFO @ 298378661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	55576940794194093776985781651593477764735333561503787039630528646460986127563	469	UVM_INFO @ 102313294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	16124848047682289403638943730852112522162012604279040024297349866484682373384	1749	UVM_INFO @ 2158288682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	81753236098492315418251969855614391175797878439232270291701486115022898367330	2465	UVM_INFO @ 740817640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	26442203109350139671656401603891959330954742658993949569356257101901323261107	3451	UVM_INFO @ 1069777094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	109525322084895814220654245062139774687353729275299203085931265093754725225444	681	UVM_INFO @ 73093860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	44428872164797530987497817064728098540772197757226276910024289015560842888403	1824	UVM_INFO @ 875773197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	71884501467129435720579515325880714787580981285588321043045324050504307742998	6933	UVM_INFO @ 505325312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	49975665963569393823923824925719593693453544105306624470245539872429576070148	6487	UVM_INFO @ 522051876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	37899477398275431192078045183912668887709304442521298554727928401322006712090	2992	UVM_INFO @ 316850194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	14307497522034529011455328487772059076720480868192598894373270811435824580688	1246	UVM_INFO @ 121434488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	29688510882519792906687084441609701587671309697311654553923508825227793154934	4494	UVM_INFO @ 1226107967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	36866244626587437582365202739198815484952931282014138045758771885910904206570	824	UVM_INFO @ 157243086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_check_error does not trigger!				34 test runs
	otp_ctrl_init_fail	14707413631750722331377344968373505747225258176782012790550925058151197078034	2783	UVM_INFO @ 377500921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	114087992524867878341229316019033232185856443421981525494548220546725404937902	1407	UVM_INFO @ 523244968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	44750686596655909855146005119457041804125191758234877817332193798129589336937	1529	UVM_INFO @ 565019794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	38778374717470545252620203167991727597397002399837405899005477195564814312766	1435	UVM_INFO @ 548031777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	3900887671317113545527391077889715676866589821114980563745661259130553087354	2283	UVM_INFO @ 1050992156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	35743820529227480121665457002446890595690517537123521730531197746145266809076	2417	UVM_INFO @ 221525181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	69126312836655464114203828810558775435347249652397853129531062538786407530417	1041	UVM_INFO @ 411637105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	62202757743707080014472425935204757911726074110904287490902712817902144789077	1417	UVM_INFO @ 2735322744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	72523994089696541262996813268159276369618226254216787603177992007150471269462	2731	UVM_INFO @ 1372978140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	36430015100581856365861923818986882046256070008834072731681472855747771280071	1983	UVM_INFO @ 970062729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	31422769280379902595916526001416641228283838968201882302916929717028913734433	1497	UVM_INFO @ 2080854592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	36466478147503960481637818772549117755094644890238706935859742962780473868856	2299	UVM_INFO @ 1719275502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	100255363004641936852684792967316175620553634159431210945979152244974504398226	1589	UVM_INFO @ 1988091099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	17459270255934491094983514887937556484396020389099275140117290133896785387153	1745	UVM_INFO @ 2056308033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	47936625759416687071333190926091934802891885235095481582347387796943444256036	1425	UVM_INFO @ 634647587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	105862289008372920666406421071805679973695781525565694259688860384672568903660	1007	UVM_INFO @ 185813206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	12317175080832422966795284510226252976204027384139486476030749743842603273448	1325	UVM_INFO @ 639971051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	38615130682505505469319701266736055771333637540868919325601849048701883586325	1021	UVM_INFO @ 1646635641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	95858678355833531254347781405942969141704410652322982920271300865954720205317	1757	UVM_INFO @ 562937299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	62425022221794666734702794366690917709922029004090338715957051782727441921639	789	UVM_INFO @ 370307322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	53037438908885674343516750081060926121999623637966529733405556955197756066521	1607	UVM_INFO @ 273271343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	55446532054391844869370034194886748094199802208867118496250842534364184814639	2041	UVM_INFO @ 1049633727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	70744403718989583035365891144591458909050294485548824487422751139591233990839	1757	UVM_INFO @ 2362256087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	9244723378161814606114622150850977271805272585355191662028503332295937397185	2273	UVM_INFO @ 460545447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	98150093027591351661498229412278360432656141016028931985460598638295167755032	2325	UVM_INFO @ 287741453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	81772823376656607233435894766288642889023030496121260256620118236464878991321	967	UVM_INFO @ 519715704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	72636287526504729804391438441589307568401824613114827759892231828709081095834	1289	UVM_INFO @ 116147367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	109999956152142763478012168482354403404832590096272810044174413221118824109560	2497	UVM_INFO @ 217446628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	47685168040892542442164429865890107878672488100945207436871405917786124439143	2607	UVM_INFO @ 1552220224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	43416578983103659901665471188233195579301338164286879233823144017073084070652	1011	UVM_INFO @ 1642934429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	115046829525986813416402587299161448516093229310526994125209117951952650225677	2223	UVM_INFO @ 256086044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	76987456861455978877776253030960492716115913462435047088992691616341992747882	1019	UVM_INFO @ 1504836932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	79233344927387429237685412153850967665868967838893899714839866028429044146885	1281	UVM_INFO @ 268916297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	85165556316942387118452896195186020841874844065087287513925272896267391955971	2199	UVM_INFO @ 396276210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.direct_access_rdata_				33 test runs
	otp_ctrl_check_fail	64069279192242391853602515198052339053826710085887503678185069761024331112944	2027	UVM_INFO @ 241157124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	24430719344509592935476270006061875778316462605695794846972496682396195127581	4693	UVM_INFO @ 5916180458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	106697369290967993994974974189352280705555602130802092298700205801390171472296	2381	UVM_INFO @ 14482471828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	36188154872064482341527674898498756313570073502131753244970570534319321712526	6575	UVM_INFO @ 243928955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	115615609601247516453374890362821438466862937013065796901853959849139740701856	1422	UVM_INFO @ 690842583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	102965117361558303558413152267500687935245657442616041881271531970441789552436	545	UVM_INFO @ 1602936095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	57446231010562693645460560238698600379054223041184223031578187356905887985135	115	UVM_INFO @ 221488239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	34369556143811124520632817328103066085143513708988025401934464835564625544233	15620	UVM_INFO @ 971509716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	20914836418188787959446683417502513778198237467288922770073849450662780154134	1447	UVM_INFO @ 974925879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	95198237508136774162212513233390047561901204336485564717339865066097643758859	3504	UVM_INFO @ 21409727296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	61041645792183839957452570620674866237300552242170154064538683064281724815882	24308	UVM_INFO @ 788077751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	77482543386451330561845660647007091185948261272505309870352197073766854694200	3226	UVM_INFO @ 1353796512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	113583918096843235679268425479699110419780861766836146451946983469436911149259	12357	UVM_INFO @ 2459789390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	71215808621128120288705750661230839025867405955018484510965925494721119166193	1169	UVM_INFO @ 426588912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	21548312832206003706393012339861074494789621145870267491480013485948817698729	2815	UVM_INFO @ 695924410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	18239409920659622567903699038418459265078128935665894180932970590453305653379	1797	UVM_INFO @ 1038364746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	92814425973476529606902757177146065070471644084509274148495368710933682583415	2310	UVM_INFO @ 765722727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	111465667533599102181279055073958588254383969404303456927883544235200589788801	229	UVM_INFO @ 626147283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	56960863570756038960088243387462980698424814782039480982811772974098286386903	135	UVM_INFO @ 345906728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	83939780303018546441927127725940272380842905527578262555438743180578298181772	273	UVM_INFO @ 61207807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	61135843185994019856178517638486196668404482282773546742989317417180691625058	1760	UVM_INFO @ 198727153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	93110466646970089692565417939090233018452612989888923743940219500293814864879	9679	UVM_INFO @ 1355674202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	57010012542702262665456527683960974882932410425702339950217420275347922635092	4135	UVM_INFO @ 1046848328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	65478018998035462288783708039583311682068242801899174920156292063166196818466	4753	UVM_INFO @ 575784470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	101528793689558914978782227339681620463254378848241612068922265493764065281989	1451	UVM_INFO @ 132531734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	79256203422404406656087420856340033535357739307941899804574773870143305715106	2264	UVM_INFO @ 544170799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	103159285678855372059688130724359742209125778278941868858767079601173749224554	155	UVM_INFO @ 611305748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	34607760143118888390142956459429890602264031978760616987532124580559217292166	341	UVM_INFO @ 50308368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	102590253214661129663472902157921345199791419757324278643523843151947605009562	7392	UVM_INFO @ 643181369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	37326848530186773134079807367957691241555636195761293709411861864031403198493	3788	UVM_INFO @ 508598941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	110499865857621767041759763028231252272827586303460722897431448360510573624290	1108	UVM_INFO @ 221558889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	70072691076690391832332434256148671226136614819747255353409565736696690554651	8964	UVM_INFO @ 11223431552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	57781398881349489898962434954211519984361862670521111776674158286615319795099	159	UVM_INFO @ 145552478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_check_error has unexpected timeout error				29 test runs
	otp_ctrl_parallel_lc_esc	42058627480112145751793123139995544973772444411574673744182802306591487234560	4714	UVM_INFO @ 1768179319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	12389729518638856160517665987171700182420364817457146390734674807016531194805	1617	UVM_INFO @ 370144065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	64849828432391347287058410452716285455716486965638738805486776526836772281251	2115	UVM_INFO @ 330463366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	95213272886564187648743468465578608596256900928477046008158205699052294337811	207	UVM_INFO @ 573046562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	103733106521885187190943148701107850766482129265465527745164949503233795795526	3054	UVM_INFO @ 348354940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	90487245997820331360512270668433619458287928498748405441058514944643537799792	1275	UVM_INFO @ 2095786121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	1090795454464663046952938599157774541737244490309098331566237188279355925929	2657	UVM_INFO @ 206448214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	14536452469521053624134010474917827105706943132167966503756326860187618729111	971	UVM_INFO @ 184461701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	39306080732467935835424764631451586736403606590520817069247951280964243074501	8168	UVM_INFO @ 2697410932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	113955625138037090863939804416850540702726952230138305451185900252500977705829	1714	UVM_INFO @ 662262347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	85154076854090353094319179684032268265011542847560788330475997176447499405741	1398	UVM_INFO @ 1724518257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	12674774021671300870295105884602185132261366224315120306337811634656469120743	851	UVM_INFO @ 1253476020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	62510128242087805164578513063999385718433204969497410509345814218762953281109	5483	UVM_INFO @ 772513302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	48809584488824719652812936912634996012849600469058141121212642241099300570698	721	UVM_INFO @ 1123390389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	16255217152671632734333250207008122376454482709809260600549197561896611396406	10255	UVM_INFO @ 15336074318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	61596970267564468665047473246965915335305526395446663914135135623921150641278	602	UVM_INFO @ 113406570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	68015405749815993367971582534275964676464479231815999545767570779589411350389	2777	UVM_INFO @ 3237631346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	133921888733322030550989172609683270961617275627200314524238286060686865482	4192	UVM_INFO @ 1188668478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	95352597235023064748951176075154088744860118312459457874584030572889454894881	5151	UVM_INFO @ 272526820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	88452887330849316460585666439902881446158463104750811908151538691947351132720	3356	UVM_INFO @ 4252812875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	52543426873234116520787644459621945175205188951972035165305568376239726504580	2585	UVM_INFO @ 1151388691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	6079338172263277229784726318681470266308960669208971704103592186261149561881	566	UVM_INFO @ 250442870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	60796507027186695162272079924633446850224856406230893120267731448897550037336	2121	UVM_INFO @ 2386754720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	102635289518889201138986671856975974231566527042914288370064253268754969192975	699	UVM_INFO @ 260033825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	14152204520399585994289590667627754670711781853132071727743137352809110425612	2266	UVM_INFO @ 261862643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	104855018698190501261392780894126512530506795224945177659307103590205311730800	637	UVM_INFO @ 1014180906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	35131713452274362646213823344513892724069280853670459718941955610814055685998	741	UVM_INFO @ 747869587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	21980287184318020665331904050786906704927849928680766176061450282233927231225	2351	UVM_INFO @ 397403549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	5061672404327914521631269311983333621179368480077879000099176834660428719012	1962	UVM_INFO @ 949166301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_macro_error does not trigger!				21 test runs
	otp_ctrl_init_fail	79981761724093552030166949884316050926310572183746808337501519712497142468216	1415	UVM_INFO @ 2258930440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	24539059627863121161791973489228868469311124106053498851062456144400712967291	2389	UVM_INFO @ 1497947525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	50013845077671697337411232631015340294553710706969261311737207130341046569191	1985	UVM_INFO @ 1761342503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	28187649577444118737361715336959916805706210879083346292471809019989295281504	1447	UVM_INFO @ 2699167512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	20311610245634475604984145756612420348119687828502950944686450472864136020084	2091	UVM_INFO @ 1470060790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	49622217176465926993073219310234886021707508784142427247855621066577074198392	1673	UVM_INFO @ 902909773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	69092854078830068548020132924913616845528054661496911972578754391374066321672	1289	UVM_INFO @ 305948643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	58817951380392615090910315280763191328243229236312183968561599274517607717130	1461	UVM_INFO @ 2512890342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	71301397596838775574910166149089682212517925087897208967663177131866698039912	1473	UVM_INFO @ 572547154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	1386085243456813305651953666311143388955259633898017025535521038705046810715	1049	UVM_INFO @ 417070548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	73373010245210827100794683851852809641511526396354520431263060308093316817384	2005	UVM_INFO @ 1413867540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	339597865998620672869971369294964902573677202581874086933421041235458385365	1193	UVM_INFO @ 238942302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	21000616493799265396603705541806652440436270085699555153229070879081877287656	1591	UVM_INFO @ 2378290178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	19775601388750621032621199024011558761360952485744898235124056217657495606632	1239	UVM_INFO @ 124122469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	30040035139589571289523129536125750990386735465303808523900313289441808833718	1125	UVM_INFO @ 1501409338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	94650684118507932520350700289900423104484591112822163596203514434146728527077	1243	UVM_INFO @ 2289099781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	67804649944241718645394123436075682925525448642126343066171823769660103416457	1707	UVM_INFO @ 274630206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	105840947811733142495716498057935668825350230907207757427959646220418111846135	1749	UVM_INFO @ 1533683859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	111667096072845914696770307260744505545823119749738958476904262392743447035020	1391	UVM_INFO @ 216140700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	22621377263413952141893848641200675589311259138915435630457745451195651153639	1479	UVM_INFO @ 1908331297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	28409494796765889700055617828646960882205348152195783574598846169266586415424	1905	UVM_INFO @ 1382196211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.intr_state				21 test runs
	otp_ctrl_stress_all_with_rand_reset	103211619298929356462204211586236585754457058899507417321278736696882657887499	1990	UVM_INFO @ 1381099058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	43992234496524224425941378746310176241948709449762326213929671306334843055839	19385	UVM_INFO @ 16250689534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	92638074056366506284343989893382048242595680698201069786976971511323154672226	9573	UVM_INFO @ 31294399221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	26330750634608258341227847513556168937616953097166996193876196734533317883925	1506	UVM_INFO @ 1579577149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	71588544795644460519988826408848383127024713917460152927448077513473121518654	871	UVM_INFO @ 192293202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	47760178506558328806516953751279918555807361593349152780255170995466982883952	5407	UVM_INFO @ 4381189713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	54450910543045261129464363352396344014509211687339260635066257317561152925096	159	UVM_INFO @ 647276078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	43926169786131301729002965158483188271104108921372159543148204709411496975875	13147	UVM_INFO @ 19516955378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	115686461864319553616683167198775697095487625233625622596568161369951006083952	2016	UVM_INFO @ 6325365752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	109633999873730091559556722813155957104076896255753324810916829186272016555670	217	UVM_INFO @ 108518786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	76246969418210883717876598292798093966052811349454485277911363222204369131405	5077	UVM_INFO @ 1516912884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	63569491598558508582924587932069376706558077795955022596723397468316753257906	1502	UVM_INFO @ 760911358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	111817656793615271747025214226520119536099587396607403906024103799731587183632	4249	UVM_INFO @ 17606357126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	99061462225421328915920530565507137276576644784300586161442819319665940250595	19569	UVM_INFO @ 1739905896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	96745157209942021559596200084519942232723961834169384069887077102679136472645	237	UVM_INFO @ 69718403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	47265056815202363711334121448894425099664020064481374116867241511038109743893	3439	UVM_INFO @ 26135106424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	7668013218174983778990630113685438445480492581044982860066053687523973150359	7188	UVM_INFO @ 24870396204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	42909389224083755324786063630528283922908072067342448781049420309861709799335	7789	UVM_INFO @ 22639212207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	39467412953470869829592837109311925447024779297222648420612769809611531214039	2729	UVM_INFO @ 1740647703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	103475591105415891196506937214825278611474157869601593756501676981412560224974	10702	UVM_INFO @ 41164638016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	11330710840652106007596578821356895636076631705484812977408940086416170609017	11666	UVM_INFO @ 17364634555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_macro_error has unexpected timeout error				15 test runs
	otp_ctrl_dai_errs	60013586167954061765924294030898079264944898482908089501963895087380136779866	3549	UVM_INFO @ 4594922536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	9667117410681688585060903432389260687716227441093289010878858117963790580973	26650	UVM_INFO @ 21713323021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	5093261965968450090296960680840918566150157606780940761902740098223079921610	1685	UVM_INFO @ 545633999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	73338205555067045546972808237428847218355512966414452697049180483902074850344	2168	UVM_INFO @ 534255855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	77939828735961591860837959007976628728127097508697682058259519495309165345706	19803	UVM_INFO @ 10961902790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	115547029296201887684639082942881364276652255354293686194753875407830987709609	2117	UVM_INFO @ 333856123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	73618264246303796412526413523731764593863462198530425950146898550390738568975	1847	UVM_INFO @ 676000682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	111580135520416506638192732463096443485590852980428126770378024923962716266875	23899	UVM_INFO @ 1395830691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	90762898115596736315957497871038032429048616530441133626873849788664428748476	55447	UVM_INFO @ 25899456772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	13305276502067590636570129768305270424108696346070127033086521368032527880396	7474	UVM_INFO @ 955728970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	56424487502385930628494294152913367539113699660201006230585441736513965883302	2870	UVM_INFO @ 3843139230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	55961619921928962093664080861259269511186398806645130661394805996911194763949	6886	UVM_INFO @ 2337336687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	28376718552838335438145633589435120186661892918812245834069271573770900329631	10255	UVM_INFO @ 8756744419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	18829647878706447398095677878419303304681339314689961807486224462362373538051	17517	UVM_INFO @ 1479843823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	85523523833418565503623717931089463443379893952956952401677955967619403169	12953	UVM_INFO @ 17443498540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:786) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =				15 test runs
	otp_ctrl_stress_all_with_rand_reset	12182767924576549982390035283432001362053318631646174337100633103421826552645	294	UVM_INFO @ 123205385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_csr_mem_rw_with_rand_reset	21564371179195313689277438397150589187900763455364908866235350385014446353254	104	UVM_INFO @ 102912826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	69370691816896375371164916617994453607655610018877834389017974714733100504049	13092	UVM_INFO @ 15127842957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	38792096868517749502404033529859491528081016412659620111254801421356753163605	98	UVM_INFO @ 107113442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	41508885127446408166881073666966014895852333049437549147504925068828588547105	5847	UVM_INFO @ 2751532359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	31472461629591525703324506874249637726428719001906148735086604567695180989317	10615	UVM_INFO @ 959979425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	105880684658972572573452046355059861528978780341732969439945488418582845974649	98	UVM_INFO @ 55246706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	46016974997527948873386412989314071518734205716746372804769673274350889283528	98	UVM_INFO @ 25822503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	83642349590056296171767360993147179104447386937630055862743984591954064891098	11723	UVM_INFO @ 6131231274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	24431462213588148451333683777420555500299977064281676592561159539026221651366	663	UVM_INFO @ 7381509184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	113433738312049598659294867951253475216012884123976952840456851653259933260930	4010	UVM_INFO @ 1289318988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	83647396858443092067142691794476245250040992185043229964012974067180249333709	99	UVM_INFO @ 427306096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	16571895690465996248012445209239070205336030508267517415887771530800181060707	23223	UVM_INFO @ 744242778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	42298212956596768193108819115109905305099925641308904074441773087583666808230	21362	UVM_INFO @ 1715683136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	14597903247178131094185116996280353546214123893672873828172883701179060346649	98	UVM_INFO @ 53556987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles				12 test runs
	otp_ctrl_stress_all	43336544280224575181070867293133979032732406659350318672662699417071647195770	22731	UVM_INFO @ 2957143937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	78025147257815217093379149145643303629447127201631364763023217587976883893692	603	UVM_INFO @ 113357195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	37009709240541777858480162983653907350781555112761127544308645827622762718989	2721	UVM_INFO @ 186319327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	39196979987574910586307755280555056931161108674844947575031659710608337539223	1202	UVM_INFO @ 104113498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	34375271354564180023706692173565057307927083009952087225573802549713845185966	4925	UVM_INFO @ 1543568757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	6846204581600806795062406147011494763314238428993126589880675071814402035838	14004	UVM_INFO @ 13635682925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	71153191869010981666046025143860049542727260560289345588932823916347013744614	3086	UVM_INFO @ 4347505793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	4101372880958205645643039194035701418775248691040142251373130815225407884263	2262	UVM_INFO @ 472563240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	62367512498588776521342187011430259123269915118346155532962280276854713067738	5155	UVM_INFO @ 415245049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	22533908128806079168320705043609023955737171415320620180378530409134887992894	9890	UVM_INFO @ 7380489900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	48475920868901669250043925063745145570067341043677173756559162191990116163820	22836	UVM_INFO @ 1386477482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	110740738919996162421394987610508791283708463688996109500292603998648340703870	30914	UVM_INFO @ 3063875145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1824) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =				12 test runs
	otp_ctrl_stress_all_with_rand_reset	53700287528025665890972274715742794506219224354586210789341201072158335661295	98	UVM_INFO @ 52839460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	39388793528348103022912714244820337878947505849942193735512543594808340065557	98	UVM_INFO @ 53293085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	2988660968864653113508944680607581226666433698112190886194043992590219440242	99	UVM_INFO @ 431318131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	17212679480590520982876701451419984317348633983965031175395558756486830904558	98	UVM_INFO @ 28656791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	77355452828440293145970349129417194959801826404239374074442370096591690006926	230	UVM_INFO @ 2314853022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	114362571357039116937873057834841109133408632994295526899386217884217643628647	6395	UVM_INFO @ 3265011416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	43861765032902824553718140112808882539052952588343243726736788190440852441569	39649	UVM_INFO @ 35323947754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	103598403979449120752020385703989126935231348240693687602276433929985593476606	6246	UVM_INFO @ 502832526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	51753753893631923259943981663303997628992718795649884671360122373748303018152	1294	UVM_INFO @ 105541208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	102916876908693003769281489564637369382067119192292118024368106271068636836083	13942	UVM_INFO @ 10834938390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	113882388243734435999440853224904529889055314586527086312551381706284523796898	40603	UVM_INFO @ 14179372302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	104962135281555251844955355979178352002507142614124121172800171465838847881076	99	UVM_INFO @ 61034894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_check_error does not trigger!				5 test runs
	otp_ctrl_background_chks	23829980957954472217903556180801464717513708090658395215841106240381337856630	5644	UVM_INFO @ 12010700588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	12892519941302501279360643284174797450898487973777504808296751872723666095875	1160	UVM_INFO @ 670182429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	76010385630138543458872505259036690769918148176877191655853680648733899329749	9083	UVM_INFO @ 8161449472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	93829261748441085648701629351408458767010071704497359364230144778806399668778	5793	UVM_INFO @ 510691325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	32729857134841030809896906159505303122778876864774177519298754630091550825725	7745	UVM_INFO @ 21887727719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred!				2 test runs
	otp_ctrl_stress_all_with_rand_reset	8192655521870657747391564729553217701667048877617899956848208225114074794280	5716	UVM_INFO @ 15253846874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	7332545198404153552080923857273972367825631656625307279540263493697891473477	15493	UVM_INFO @ 15463827639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_bus_integ_error) did not fire in * cycles.				2 test runs
	otp_ctrl_tl_intg_err	106791602920929432537366925041273858185293415033763336209180829613644598423388	240	UVM_INFO @ 7934886003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_tl_intg_err	69580629710939289172189356252126295173566611066819305420726903177952362775079	180	UVM_INFO @ 281050053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	otp_ctrl_stress_all_with_rand_reset	32666603129482557904910962782978995783607450282582450572864264529548174508581	2000	UVM_INFO @ 14290359934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	20641592970473729956415566003420325391201969962864015154540219821565409770115	3392	UVM_INFO @ 15296499397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_check_error) did not fire in * cycles.				1 test run
	otp_ctrl_sec_cm	49641512380967198719883399487697273363517009052376423697065591017721620594316	545	UVM_INFO @ 8084416279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	otp_ctrl_stress_all_with_rand_reset	47915437281018435705634933724231542120092486493973808584847905890498798930539	None
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen				1 test run
	otp_ctrl_stress_all_with_rand_reset	58971217559526905766060630213325829674269192087144648506333027836949880116335	4541	UVM_INFO @ 24804012542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed				1 test run
	otp_ctrl_stress_all_with_rand_reset	114827366979370155436233740783754020001288634642598935545628822393684039212988	7869	UVM_INFO @ 33812955850 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 33814122519 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 33830122551 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 33830789219 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1