Simulation Results: pwrmgr

 
12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.91 %
  • code
  • 95.75 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.38 %
  • cond
  • 96.32 %
  • toggle
  • 90.96 %
  • FSM
  • 96.00 %
Validation stages
V1
95.65%
V2
89.05%
V2S
68.70%
V3
25.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 1.000s 27.034us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.970s 25.792us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.980s 18.148us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.910s 213.057us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.020s 64.063us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
pwrmgr_csr_mem_rw_with_rand_reset 3600.039s 0.000us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.980s 18.148us 5 5 100.00
pwrmgr_csr_aliasing 1.020s 64.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.720s 272.271us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.720s 272.271us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.470s 44.914us 10 10 100.00
pwrmgr_lowpower_invalid 1.090s 44.443us 10 10 100.00
reset 14 20 70.00
pwrmgr_reset 3.540s 1000.000us 9 10 90.00
pwrmgr_reset_invalid 3600.041s 0.000us 5 10 50.00
main_power_glitch_reset 9 10 90.00
pwrmgr_reset 3.540s 1000.000us 9 10 90.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.870s 305.550us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.580s 245.078us 10 10 100.00
disable_rom_integrity_check 7 10 70.00
pwrmgr_disable_rom_integrity_check 1.840s 1000.000us 7 10 70.00
stress_all 4 10 40.00
pwrmgr_stress_all 10800.052s 0.000us 4 10 40.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.980s 63.217us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.950s 130.801us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.950s 130.801us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.970s 25.792us 1 1 100.00
pwrmgr_csr_rw 0.980s 18.148us 5 5 100.00
pwrmgr_csr_aliasing 1.020s 64.063us 1 1 100.00
pwrmgr_same_csr_outstanding 1.330s 40.886us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.970s 25.792us 1 1 100.00
pwrmgr_csr_rw 0.980s 18.148us 5 5 100.00
pwrmgr_csr_aliasing 1.020s 64.063us 1 1 100.00
pwrmgr_same_csr_outstanding 1.330s 40.886us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 4 30 13.33
pwrmgr_tl_intg_err 3600.046s 0.000us 3 25 12.00
pwrmgr_sec_cm 3600.059s 0.000us 1 5 20.00
prim_count_check 1 5 20.00
pwrmgr_sec_cm 3600.059s 0.000us 1 5 20.00
prim_fsm_check 1 5 20.00
pwrmgr_sec_cm 3600.059s 0.000us 1 5 20.00
sec_cm_bus_integrity 3 25 12.00
pwrmgr_tl_intg_err 3600.046s 0.000us 3 25 12.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.440s 775.387us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.870s 305.550us 10 10 100.00
pwrmgr_repeat_wakeup_reset 3.700s 885.834us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.320s 76.973us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.920s 105.399us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 1 5 20.00
pwrmgr_sec_cm 3600.059s 0.000us 1 5 20.00
sec_cm_fsm_sparse 1 5 20.00
pwrmgr_sec_cm 3600.059s 0.000us 1 5 20.00
sec_cm_fsm_terminal 1 5 20.00
pwrmgr_sec_cm 3600.059s 0.000us 1 5 20.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 1.010s 51.856us 10 10 100.00
sec_cm_main_pd_rst_local_esc 0 10 0.00
pwrmgr_glitch 3600.041s 0.000us 0 10 0.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.900s 312.778us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.980s 18.148us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.980s 18.148us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 4 10 40.00
pwrmgr_escalation_timeout 1.250s 106.309us 4 10 40.00
stress_all_with_rand_reset 1 10 10.00
pwrmgr_stress_all_with_rand_reset 3600.046s 0.000us 1 10 10.00

Error Messages

   Test seed line log context
Job timed out after * minutes 51 test runs
pwrmgr_glitch 11251596195681477798344988836513278999638061568036201689401896679426349067129 None
pwrmgr_tl_intg_err 36194509523648068197609690485158029526459307002159625422393829733237406202674 None
pwrmgr_sec_cm 71920282718800536869999515527947681788977807095732259114325034925565516643150 None
pwrmgr_stress_all_with_rand_reset 104153115046385310088842347842035126995182700945375718840315734973357614735124 None
pwrmgr_glitch 102915265654629430512347214115173918007752734652903209504427467717013352321409 None
pwrmgr_tl_intg_err 53735629244539944076614683681904127781445478781386269901928725989399218809618 None
pwrmgr_sec_cm 76561239663876559606977839809809974548845126147760966340387738298866263995118 None
pwrmgr_stress_all_with_rand_reset 109218536439642949923159057967168842867136675310079007126986971591819711699654 None
pwrmgr_glitch 17416438521442905542727922353894389123765842166999922541986726094768317340423 None
pwrmgr_tl_intg_err 62916439772431872155889685705739035585273993040770793801468524288935345007805 None
pwrmgr_sec_cm 102357816272926773637366149595807472122807007056531274383191231666281771126787 None
pwrmgr_stress_all_with_rand_reset 81734965952130340994146486019605597319975679578075605773843220673502012820881 None
pwrmgr_stress_all 16553659713181561378138133892064224346657038781884995232143815641343913320949 None
pwrmgr_csr_mem_rw_with_rand_reset 72216964541841222327714440748373300150735922604588536306646722710183600048850 None
pwrmgr_glitch 89738340713956672464798864263630643379160501801042228071472843258174832732296 None
pwrmgr_reset_invalid 111262233198565561498885608600514972709499860766665776933380798896291265628938 None
pwrmgr_stress_all_with_rand_reset 34361178172221817618663048949724143220263194050763988804304118464463508478320 None
pwrmgr_stress_all 100404380988353702132940443869494469147634486500806013964460691394579865625459 None
pwrmgr_glitch 3746554592315372625402635318401711357581292323567286574775664278013671583451 None
pwrmgr_tl_intg_err 106052240760654862037190792183315307380057711757809494751554483992783275376951 None
pwrmgr_sec_cm 90278373455936614116496864098020046567684518538545601969537393251581957203488 None
pwrmgr_stress_all_with_rand_reset 106076929995930859813979851320074230417429918459041118719247603800414546138481 None
pwrmgr_stress_all 5047751699926164317051809485492983773540910580141837706653386907493304037086 None
pwrmgr_glitch 73840120635692206749020580101883398470026848557843409545053580830691863696269 None
pwrmgr_tl_intg_err 12846520065704639272761516806818165685839451317871504271647828564428481679985 None
pwrmgr_glitch 84348529821058580311845911041961684222194849004963044539765498449193936473010 None
pwrmgr_glitch 50301826041398265509402911714724239591970683946285962983039976758758201061480 None
pwrmgr_tl_intg_err 51254172982038062907372953715037438764815242760850445620537535105819593858079 None
pwrmgr_stress_all_with_rand_reset 29867880719404141925611384643367321271279581782731206923669953691729085611771 None
pwrmgr_glitch 83857891436889635788283568470512783247664354840757265346342198831221406965580 None
pwrmgr_tl_intg_err 46856230611213689013682625670036494723320395172312727772903774698992394775928 None
pwrmgr_stress_all_with_rand_reset 89976553811949235638136203620594046418802806482429730942042761206839586713695 None
pwrmgr_stress_all 67281985177282070247751581600030312773084035518797694830850234198005199777558 None
pwrmgr_glitch 48041901118848428463521774886621275053325701145503182851472931118471121792620 None
pwrmgr_tl_intg_err 82039276567154152399487808256724287981516739043391236080011368330276969628739 None
pwrmgr_stress_all_with_rand_reset 16945209067315869808916692460171108015994049794351487030432620158144711919944 None
pwrmgr_stress_all 17004369437923803123753235249445476922055816856272896994906278341514159635632 None
pwrmgr_tl_intg_err 11987273566658102334563717951819829193213657345508160082757961680391333736895 None
pwrmgr_tl_intg_err 109293817065528501415126716201136862287983115108396292042658393808371536699184 None
pwrmgr_tl_intg_err 56114868685534107191580061300764671043640426622308660276341794844616307824129 None
pwrmgr_tl_intg_err 22568570036869422497844837761233969253017923239157027788707422417377695600381 None
pwrmgr_tl_intg_err 114439199904079522314626718796442347597808823613669485009661864205806267042669 None
pwrmgr_tl_intg_err 7205178582972774565609925450913783861271292074152854035638994392313715748484 None
pwrmgr_tl_intg_err 32640149558483025543282721399920355793212507042373067657430282289926165207192 None
pwrmgr_tl_intg_err 104326805922149197873892036893775312946514795929686788460125277161608670797681 None
pwrmgr_tl_intg_err 95907189568247632204423898691910169721149954125316309996742267055451886283685 None
pwrmgr_tl_intg_err 61433431676089345678854693609352266251800911382417747493174452107958932358563 None
pwrmgr_tl_intg_err 113926551824190751411347756066561834970802721009708833210541344887056285752482 None
pwrmgr_tl_intg_err 108227954590424603720169329523421397007234972080226354534123238977310853119304 None
pwrmgr_tl_intg_err 104136611026464065826176975695496556070789714369013342726273586299091590012797 None
pwrmgr_tl_intg_err 2934749446325867939696823425355160913898746907979026659008505316019302918248 None
Offending '((!clk_en) || status)' 6 test runs
pwrmgr_escalation_timeout 658915427795170135724241609262801930065677158780062284060348579599841309066 85
UVM_ERROR @ 101263748 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 101263748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 87629791594324114137538604032906471926223185952893037026504929740394372721915 85
UVM_ERROR @ 371446998 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 371446998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 78190410155160912959466524831578735330421655200848668718953269970641036695024 85
UVM_ERROR @ 370690632 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 370690632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 17867437035169231055995799000874744327087475349637982328870949029444710747532 85
UVM_ERROR @ 98806151 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 98806151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 84076322298615826098254410588690070882088098615815376054157000551500043291816 85
UVM_ERROR @ 187748251 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 187748251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 1381318232102941780420408922916793359017369174407352039800454353210789962508 85
UVM_ERROR @ 102108625 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 102108625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
pwrmgr_reset 26222335622078492311931027050138867056757346092596510059380772758820582121389 115
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 57322474883130822033811892319463840017824201765408818152426476195454125101242 96
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 60561317672526619339011166043400036068126573202033223407537955616702297930532 147
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 23354606319742728809277466957543982648088671385683607694046409175046875775877 82
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitNvmShutDown 2 test runs
pwrmgr_reset_invalid 57317180099397130921343333291371652124338461018530606189936171256782702900833 115
UVM_INFO @ 31298031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset_invalid 5791600038684804375545363863345990304285694414089842364123316877538452952601 93
UVM_INFO @ 37748235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit 1 test run
pwrmgr_reset_invalid 31601626571729378341425680460292974634746788800142464045464318860755038574075 141
UVM_INFO @ 76687595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1209) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
pwrmgr_stress_all_with_rand_reset 72684444572080187488658043010811836127270108672184975672179608634212435641184 433
UVM_INFO @ 832532197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 83261262976789400081725466554001150788127723983738701221160954939585550416737 177
UVM_INFO @ 10063634268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitResetPrep 1 test run
pwrmgr_reset_invalid 61382776447796290096828398312250818152598628050448044211723854135445511657254 90
UVM_INFO @ 44834529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---