Simulation Results: rom_ctrl/192kb

 
12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.49 %
  • code
  • 98.51 %
  • assert
  • 97.68 %
  • func
  • 99.28 %
  • line
  • 99.21 %
  • branch
  • 99.64 %
  • cond
  • 98.37 %
  • toggle
  • 95.34 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.77%
V2S
100.00%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 33.490s 1137.600us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 33.240s 89.083us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 17.660s 52.404us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 17.990s 81.972us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 17.790s 104.424us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 17.930s 53.471us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 17.660s 52.404us 5 5 100.00
rom_ctrl_csr_aliasing 17.790s 104.424us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 17.460s 97.620us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 18.430s 56.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 29.440s 994.284us 0 2 0.00
stress_all 19 20 95.00
rom_ctrl_stress_all 10800.122s 0.000us 19 20 95.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 60.860s 2076.042us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 18.780s 53.986us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 36.300s 1031.340us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 36.300s 1031.340us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 33.240s 89.083us 1 1 100.00
rom_ctrl_csr_rw 17.660s 52.404us 5 5 100.00
rom_ctrl_csr_aliasing 17.790s 104.424us 1 1 100.00
rom_ctrl_same_csr_outstanding 19.410s 64.195us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 33.240s 89.083us 1 1 100.00
rom_ctrl_csr_rw 17.660s 52.404us 5 5 100.00
rom_ctrl_csr_aliasing 17.790s 104.424us 1 1 100.00
rom_ctrl_same_csr_outstanding 19.410s 64.195us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 938.670s 123156.411us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 125.370s 2103.956us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 3107.910s 455.014us 5 5 100.00
rom_ctrl_tl_intg_err 664.730s 746.787us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 3107.910s 455.014us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 3107.910s 455.014us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 938.670s 123156.411us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 938.670s 123156.411us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 938.670s 123156.411us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 938.670s 123156.411us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 938.670s 123156.411us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 3107.910s 455.014us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 3107.910s 455.014us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 33.490s 1137.600us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 33.490s 1137.600us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 33.490s 1137.600us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 664.730s 746.787us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 938.670s 123156.411us 20 20 100.00
rom_ctrl_kmac_err_chk 60.860s 2076.042us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 938.670s 123156.411us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 938.670s 123156.411us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 938.670s 123156.411us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 125.370s 2103.956us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 3107.910s 455.014us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
rom_ctrl_stress_all_with_rand_reset 390.940s 28479.439us 19 20 95.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 63526453029502045800630810455141051889786295249175736423287275030050548490095 85
UVM_INFO @ 16222528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 78635240659263823496303411927487593359363533821801577765966013501655210070669 85
UVM_INFO @ 994283835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rom_ctrl_stress_all_with_rand_reset 12375795838801580569296002573257137273667314557688754730977773482332629081925 86
UVM_INFO @ 85875991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_stress_all 99198459035262904876575688504230566967698012615964939686344073167041615129654 None