Simulation Results

Simulation Results: rv_timer

12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.30 %

code
94.66 %

assert
98.41 %

func
98.82 %

line
100.00 %

branch
100.00 %

cond
100.00 %

toggle
78.66 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%
V3		52.50%

33/33 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
random				20	20	100.00
	rv_timer_random	2.070s	350.229us	20	20	100.00
csr_hw_reset				1	1	100.00
	rv_timer_csr_hw_reset	0.850s	15.028us	1	1	100.00
csr_rw				5	5	100.00
	rv_timer_csr_rw	0.880s	24.171us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_timer_csr_bit_bash	1.750s	98.839us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_timer_csr_aliasing	0.890s	22.647us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_timer_csr_mem_rw_with_rand_reset	1.440s	25.364us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_timer_csr_rw	0.880s	24.171us	5	5	100.00
	rv_timer_csr_aliasing	0.890s	22.647us	1	1	100.00

127/127 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
random_reset				20	20	100.00
	rv_timer_random_reset	15.660s	82118.156us	20	20	100.00
disabled				20	20	100.00
	rv_timer_disabled	3.900s	1760.034us	20	20	100.00
cfg_update_on_fly				10	10	100.00
	rv_timer_cfg_update_on_fly	739.430s	3366017.336us	10	10	100.00
no_interrupt_test				10	10	100.00
	rv_timer_cfg_update_on_fly	739.430s	3366017.336us	10	10	100.00
stress				20	20	100.00
	rv_timer_stress_all	10.390s	7266.115us	20	20	100.00
alert_test				10	10	100.00
	rv_timer_alert_test	0.880s	10.995us	10	10	100.00
intr_test				10	10	100.00
	rv_timer_intr_test	0.890s	13.840us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_timer_tl_errors	3.260s	168.869us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_timer_tl_errors	3.260s	168.869us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_timer_csr_hw_reset	0.850s	15.028us	1	1	100.00
	rv_timer_csr_rw	0.880s	24.171us	5	5	100.00
	rv_timer_csr_aliasing	0.890s	22.647us	1	1	100.00
	rv_timer_same_csr_outstanding	1.100s	36.731us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_timer_csr_hw_reset	0.850s	15.028us	1	1	100.00
	rv_timer_csr_rw	0.880s	24.171us	5	5	100.00
	rv_timer_csr_aliasing	0.890s	22.647us	1	1	100.00
	rv_timer_same_csr_outstanding	1.100s	36.731us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_timer_sec_cm	1.260s	350.952us	5	5	100.00
	rv_timer_tl_intg_err	1.690s	312.760us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_timer_tl_intg_err	1.690s	312.760us	25	25	100.00

21/40 passed

52.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
min_value				2	10	20.00
	rv_timer_min	1.450s	53.781us	2	10	20.00
max_value				0	10	0.00
	rv_timer_max	1.150s	87.787us	0	10	0.00
stress_all_with_rand_reset				19	20	95.00
	rv_timer_stress_all_with_rand_reset	61.110s	25489.531us	19	20	95.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*])				9 test runs
	rv_timer_max	10034090520992593271013195746082752460350635454999338449011673657029753560243	81	UVM_INFO @ 44766198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_max	63947571343954688319224052277317830822008378568206817518298664117007241542510	82	UVM_INFO @ 87786861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_max	4227147129135017445534484287121217713147559799491286722406633173800041404521	81	UVM_INFO @ 42586610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_max	18962510172667581305344378060212125336371949423508020284359899223976360279986	81	UVM_INFO @ 170835125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_max	43164651949706887104444115324193773230001072576328745364112708627104154407163	81	UVM_INFO @ 42536175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_max	9412087113392553868295404516406532930794223851946926256073603977227820795701	81	UVM_INFO @ 104125147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_max	50054049861059274589117724764199002284945684712488546058224743663018976724913	81	UVM_INFO @ 43001819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_max	6529589174884467122520740498907208748556672265004626409556096891268520367322	81	UVM_INFO @ 178264344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_max	4689341765366471127226971748386395190803062568063054110385091021433542188376	81	UVM_INFO @ 43155467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=) ==				8 test runs
	rv_timer_min	48701351309222104068435026785368098458807703013437867223996987677864075499385	83	UVM_INFO @ 60376719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_min	93296416759308831680905734437475952124878636235011024376838069993712412513525	81	UVM_INFO @ 70592848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_min	68234744707496980514237860290061657191289952438402450063025094965646552299755	83	UVM_INFO @ 72926375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_min	45933551731780219783374362771963235196234609438000925237903302561273272921481	83	UVM_INFO @ 205345683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_min	45920897210004429211311869202617176803180732716319015866318143385245381059308	81	UVM_INFO @ 228623249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_min	1700133622198702970008978002689513725045875835997266281045963052260802720299	81	UVM_INFO @ 215099791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_min	101971367088222637976752056338481565352942788958389795975264209089331965455649	83	UVM_INFO @ 405573907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_min	63380584620244314202249777997310947280349266414182107748411996432192598599212	81	UVM_INFO @ 53781318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [rv_timer_common_vseq] wait timeout occurred!				1 test run
	rv_timer_stress_all_with_rand_reset	107259214441663291163732698216167686385605127746886139217960069384308879513227	119	UVM_INFO @ 10128832227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:342) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [] vs [*])				1 test run
	rv_timer_max	81751429865583919844651871121613577926250168699787810613735165619441413009725	81	UVM_INFO @ 184911129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---