| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 2671.664us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 16.409us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 13.791us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 4.000s | 995.264us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 1.000s | 67.517us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 5.000s | 1988.708us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 13.791us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 67.517us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 458.000s | 143203.667us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 161.000s | 20299.505us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 60.000s | 32103.967us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 237.000s | 8511.594us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 272.000s | 30871.280us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 135.000s | 69468.540us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 95.000s | 92236.499us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 55.000s | 7744.252us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 7.000s | 1000.530us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 334.000s | 47988.922us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 7.000s | 1361.289us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 7.000s | 2775.670us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 7.000s | 2403.468us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 34.000s | 10557.582us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 7.000s | 368.695us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 2671.664us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 7.000s | 1000.530us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 135.000s | 69468.540us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 1131.000s | 76857.836us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 54.548us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 8.000s | 692.205us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 8.000s | 692.205us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 16.409us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 13.791us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 67.517us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 28.827us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 16.409us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 13.791us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 67.517us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 28.827us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 44.000s | 7055.958us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 732.584us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 605.941us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 732.584us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 605.941us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 34.000s | 10557.582us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 34.000s | 10557.582us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 13.791us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 55.000s | 7744.252us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 55.000s | 7744.252us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 55.000s | 7744.252us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 95.000s | 92236.499us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3602.054s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 44.000s | 7055.958us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 2671.664us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 2671.664us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 55.000s | 7744.252us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 732.584us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 95.000s | 92236.499us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 732.584us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 732.584us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 2671.664us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 732.584us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 51.000s | 1282.850us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 12974266537906407295158299384645021458013170443752603400089924127370154642487 | None | ||
| sram_ctrl_mubi_enc_err | 24184418873368971808489359467366446935291609391027000716892890952642111059793 | None | ||
| sram_ctrl_readback_err | 6759182123861540591635870467622117255025351516459796227493043950431289232559 | None | ||
| sram_ctrl_mubi_enc_err | 96225568085325165278666084171999529020526249725137139187368244296627543771476 | None | ||
| sram_ctrl_readback_err | 7863730676312992836711893278273891755463035867229813287034401831907387070948 | None | ||
| sram_ctrl_mubi_enc_err | 93183008842518583705576172290656515912913934127869751299624403273399784659646 | None | ||
| sram_ctrl_readback_err | 17049178805080568250825150384978962431611426061563982909628548144941562081760 | None | ||
| sram_ctrl_mubi_enc_err | 43445864502453895699669602964099062064702150910306772249831696692897504357199 | None | ||
| sram_ctrl_readback_err | 107744869999704523210373325295995398109483954071757093859484991021956616822188 | None | ||
| sram_ctrl_mubi_enc_err | 52408314978420296160845362236522170149831397930860019243338936431212292812741 | None | ||
| sram_ctrl_readback_err | 85889927965277509083713456086861435508476159532700694648840115743500428313845 | None | ||
| sram_ctrl_mubi_enc_err | 101854745419963898128573424731733464030576301134767711127254460558459441391418 | None | ||
| sram_ctrl_readback_err | 15695470605517549063512902373248785725312399107938396168641633160438277659042 | None | ||
| sram_ctrl_mubi_enc_err | 64937697258772315184946760754349453814374625912479634982173880052508010630072 | None | ||
| sram_ctrl_readback_err | 15831209821089835710392580823708398427726494104362149177440423678428262864613 | None | ||
| sram_ctrl_mubi_enc_err | 45933180287603502637727327273589195265284096829236098193946804968442970380350 | None | ||